Semiconductor device having asymmetric fin-shaped pattern

Patent metadata

Field	Value
Publication number	US-9601628-B2
Application number	US-201514983904-A
Country	US
Kind code	B2
Filing date	Dec 30, 2015
Priority date	Jan 15, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

Semiconductor devices are provided including a first fin-shaped pattern having first and second sidewalls facing one another and a field insulating film contacting at least a portion of the first fin-shaped pattern. The first fin-shaped pattern includes a lower portion of the first fin-shaped pattern contacting the field insulating film; an upper portion of the first fin-shaped pattern not contacting the field insulating film; a first boundary between the lower portion of the first fin-shaped pattern and the upper portion of the first fin-shaped pattern; and a first fin center line perpendicular to the first boundary and meeting the top of the upper portion of the first fin-shaped pattern. The first sidewall of the upper portion of the first fin-shaped pattern and the second sidewall of the upper portion of the first fin-shaped pattern are asymmetric with respect to the first fin center line.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first fin-shaped pattern including first and second sidewalls facing one another; and
a field insulating film contacting at least a portion of the first fin-shaped pattern,
wherein the first fin-shaped pattern comprises:
a lower portion of the first fin-shaped pattern contacting the field insulating film;
an upper portion of the first fin-shaped pattern not contacting the field insulating film;
a first boundary between the lower portion of the first fin-shaped pattern and the upper portion of the first fin-shaped pattern; and
a first fin center line perpendicular to the first boundary and meeting the top of the upper portion of the first fin-shaped pattern;

wherein the first sidewall of the upper portion of the first fin-shaped pattern and the second sidewall of the upper portion of the first fin-shaped pattern are asymmetric with respect to the first fin center line;
wherein, in the upper portion of the first fin-shaped pattern having a first distance from the first boundary, a slope of the first sidewall is defined by a first slope, a slope of the second sidewall is defined by a second slope, a width between the first fin center line and the first sidewall is defined by a first width, and a width between the first fin center line and the second sidewall is defined by a second width; and
wherein one of the first slope and the second slope are different from each other and the first width and the second width are different from each other.

2. The semiconductor device of claim 1 :
wherein the first sidewall includes a first inflection point, and the second sidewall includes a second inflection point; and
wherein a distance from the first boundary to the first inflection point is different from a distance from the first boundary to the second inflection point.

3. The semiconductor device of claim 2 , wherein the first inflection point and the second inflection point are located over an upper surface of the field insulating film.

4. The semiconductor device of claim 1 , further comprising:
a second fin-shaped pattern including third and fourth sidewalls facing one another and being immediately adjacent to the first fin-shaped pattern;
a first trench between the second sidewall of the first fin-shaped pattern and the third sidewall of the second fin-shaped pattern, the second sidewall and the third sidewall facing one another; and
a second trench adjacent to the first sidewall of the first fin-shaped pattern and the fourth sidewall of the second fin-shaped pattern,
wherein the field insulating film fills at least a portion of the first trench and at least a portion of the second trench;
wherein the second fin-shaped pattern comprises:
a lower portion of the second fin-shaped pattern contacting the field insulating film;
an upper portion of the second fin-shaped pattern not contacting the field insulating film;
a second boundary between the lower portion of the second fin-shaped pattern and the upper portion of the second fin-shaped pattern; and
a second fin center line perpendicular to the second boundary and meeting the to of the upper portion of the second fin-shaped pattern, and

wherein the third sidewall of the upper portion of the second fin-shaped pattern and the fourth sidewall of the upper portion of the second fin-shaped pattern are asymmetric with respect to the second fin center line.

5. The semiconductor device of claim 4 :
wherein the first trench defines the first fin-shaped pattern and the second fin-shaped pattern;
wherein a first depth of the first trench is smaller than a second depth of the second trench;
wherein a field center line located away from the first fin center line and the second fin center line by a same distance is defined between the first fin center line and the second fin center line; and
wherein the second sidewall of the upper portion of the first fin-shaped pattern and the third sidewall of the upper portion of the second fin-shaped pattern are symmetric with respect to the field center line.

6. The semiconductor device of claim 5 :
wherein the first trench is on both sides of the second fin-shaped pattern;
wherein the semiconductor device further comprises a third fin-shaped pattern defined by the first trench and including fifth and sixth sidewalls facing one another between the second fin-shaped pattern and the second trench;
wherein the third fin-shaped pattern comprises:
a lower portion of the third fin-shaped pattern contacting the field insulating film;
an upper portion of the third fin-shaped pattern not contacting the field insulating film;
a third boundary between the lower portion of the third fin-shaped pattern and the upper portion of the third fin-shaped pattern; and
a third fin center line perpendicular to the third boundary and meeting the top of the upper portion of the third fin-shaped pattern; and

wherein the fifth sidewall of the upper portion of the third fin-shaped pattern and the sixth sidewall of the upper portion of the third fin-shaped pattern are asymmetric with respect to the third fin center line.

7. The semiconductor device of claim 4 :
wherein a first depth of the first trench is equal to or smaller than a second depth of the second trench; and
wherein the first trench and the second trench define an active region.

8. The semiconductor device of claim 1 , further comprising:
a second fin-shaped pattern comprising third and fourth sidewalls facing one another, wherein the second fin-shaped pattern comprises:
a lower portion of the second fin-shaped pattern contacting the field insulating film;
an upper portion of the second fin-shaped pattern not contacting the field insulating film;
a second boundary between the lower portion of the second fin-shaped pattern and the upper portion of the second fin-shaped pattern; and
a second fin center line perpendicular to the second boundary and meeting the to of the upper portion of the second fin-shaped pattern; and

wherein the third sidewall of the second fin-shaped pattern and the fourth sidewall of the second fin-shaped pattern are symmetric with respect to the second fin center line.

9. The semiconductor device of claim 1 , further comprising a gate electrode crossing the first fin-shaped pattern.

10. A semiconductor device, comprising:
a first trench having a first depth and defining a first fin-shaped pattern; a second trench having a second depth, larger than the first depth, at both sides of the first fin-shaped pattern; and
a field insulating film filling at least a portion of the first trench and at least a portion of the second trench,
wherein the first fin-shaped pattern comprises:
a lower portion of the first fin-shaped pattern contacting the field insulating film;
an upper portion of the first fin-shaped pattern not contacting the field insulating film;
a first boundary between the lower portion of the first fin-shaped pattern and the upper portion of the first fin-shaped pattern;
a first fin center line perpendicular to the first boundary and meeting the top of the upper portion of the first fin-shaped pattern;
wherein the first sidewall of the first fin-shaped pattern and the second sidewall of the first fin-shaped pattern are asymmetric with respect to the first fin center line;
wherein, in the first fin-shaped pattern having a first distance from the first boundary, a slope of the first sidewall is defined by a first slope, a slope of the second sidewall is defined by a second slope, a width between the first fin center line and the first sidewall is defined by a first width, and a width between the first fin center line and the second sidewall is defined by a

Assignees

• You Jung-Gun
• Park Se-Wan
• Sung Baik-Min
• Jeong Bo-Cheol
• Samsung Electronics Co Ltd

Inventors

• You Jung-Gun
• Park Se-Wan
• Sung Baik-Min
• Jeong Bo-Cheol

Classifications

• H10D30/792

  comprising applied insulating layers, e.g. stress liners · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H01L27/0886

  Electricity · mapped topic

• H01L29/7851

  Electricity · mapped topic