Low voltage embedded memory having cationic-based conductive oxide element

Patent metadata

Field	Value
Publication number	US-9224461-B2
Application number	US-201213686507-A
Country	US
Kind code	B2
Filing date	Nov 27, 2012
Priority date	Nov 27, 2012
Publication date	Dec 29, 2015
Grant date	Dec 29, 2015

Abstract

Low voltage embedded memory having cationic-based conductive oxide elements is described. For example, a material layer stack for a memory element includes a first conductive electrode. A cationic-based conductive oxide layer is disposed on the first conductive electrode. The cationic-based conductive oxide layer has a plurality of cation vacancies therein. A second electrode is disposed on the cationic-based conductive oxide layer.

First claim

What is claimed is:

1. A material layer stack for a memory element, the material layer stack comprising:
a first conductive electrode;
a cationic-based conductive oxide layer disposed on the first conductive electrode, the cationic-based conductive oxide layer having a plurality of cation vacancies therein; and
a second electrode disposed on the cationic-based conductive oxide layer.

2. The material layer stack of claim 1 , wherein the cationic-based conductive oxide layer comprises a material having cation-based mobility.

3. The material stack of claim 2 , wherein the material having cation-based mobility has lithium (Li + ), sodium (Na + ) or silver (Ag + ) mobility.

4. The material stack of claim 3 , wherein the material having cation-based mobility has lithium (Li + ) mobility and is selected from the group consisting of LiCoO 2 , LiMnO 2 , Li 4 TiO 12 , LiNiO 2 , LiNbO 3 , Li 3 N:H and LiTiS 2 .

5. The material stack of claim 3 , wherein the material having cation-based mobility has sodium (Na + ) mobility and is Na β-alumina.

6. The material stack of claim 3 , wherein the material having cation-based mobility has silver (Ag + ) mobility and is selected from the group consisting of AgI, RbAg 4 I 5 and AgGeAsS 3 .

7. The material layer stack of claim 1 , wherein the resistivity of the cationic-based conductive oxide layer is approximately in the range of 10 mOhm cm-10 kOhm when measured at a low field of approximately 0.1V.

8. The material layer stack of claim 1 , wherein the second electrode comprises a material that is an intercalation host for cations.

9. The material layer stack of claim 8 , wherein the material is selected from the group consisting of graphite and a metal chalcogenide.

10. The material layer stack of claim 1 , wherein the first electrode is a noble metal electrode.

11. The material layer stack of claim 10 , wherein the noble metal electrode comprises a material selected from the group consisting of palladium (Pd) and platinum (Pt).

Assignees

• Karpov Elijah V
• Doyle Brian S
• Kuo Charles C
• Chau Robert S
• Intel Corp

Inventors

• Karpov Elijah V
• Doyle Brian S
• Kuo Charles C
• Chau Robert S

Classifications

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C2013/0073

  Write using bi-directional cell biasing · CPC title

• H01L45/145

  Electricity · mapped topic

• H01L45/085

  Electricity · mapped topic