Blocking oxide in memory opening integration scheme for three-dimensional memory structure

Patent metadata

Field	Value
Publication number	US-9601508-B2
Application number	US-201514921385-A
Country	US
Kind code	B2
Filing date	Oct 23, 2015
Priority date	Apr 27, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of a memory opening, all surfaces of the memory opening are provided as silicon oxide surfaces by formation of at least one silicon oxide portion. A silicon nitride layer is formed in the memory opening. After formation of a memory stack structure, backside recesses can be formed employing the silicon oxide portions as an etch stop. The silicon oxide portions can be subsequently removed employing the silicon nitride layer as an etch stop. Physically exposed portions of the silicon nitride layer can be removed selective to the memory stack structure. Damage to the outer layer of the memory stack structure can be minimized or eliminated by successive use of etch stop structures. Electrically conductive layers can be subsequently formed in the backside recesses.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers and located over a substrate;
a memory stack structure extending through the alternating stack and comprising, from outside to inside, a blocking dielectric, memory elements, a tunneling dielectric, and a semiconductor channel; and
annular silicon nitride spacers located at each level of the insulating layers, vertically spaced from one another, and contacting an outer sidewall of the blocking dielectric.

2. The three-dimensional memory device of claim 1 , further comprising annular silicon oxide spacers located at each level of the insulating layers, vertically spaced from one another, and contacting an outer sidewall of a respective silicon nitride spacer.

3. The three-dimensional memory device of claim 2 , wherein each of the annular silicon oxide spacers contacts a sidewall of a respective insulating layer.

4. The three-dimensional memory device of claim 2 , wherein the annular silicon oxide spacers include carbon at an atomic concentration greater than 1.0×10 19 /cm 3 .

5. The three-dimensional memory device of claim 1 , further comprising spacer blocking dielectric portions which are located between the silicon nitride spacers adjacent to the electrically conductive layers.

6. The three-dimensional memory device of claim 5 , wherein the blocking dielectric comprises the spacer blocking dielectric portions which contact a blocking dielectric layer to form a combined blocking dielectric which is thinner adjacent to the insulating layers than adjacent to the electrically conductive layers.

7. The three-dimensional memory device of claim 1 , wherein the annular silicon nitride spacers have a lateral concentration gradient such that oxygen concentration in each of the annular silicon nitride spacers increases with a lateral distance from a respective inner sidewall thereof.

8. The three-dimensional memory device of claim 1 , wherein the annular silicon nitride spacers have a homogeneous composition throughout.

9. The three-dimensional memory device of claim 1 , further comprising a single crystal silicon epitaxial channel portion underlying the memory stack structure and contacting the semiconductor channel which comprises polysilicon.

10. The three-dimensional memory device of claim 9 , wherein an interface between the epitaxial channel portion and one of the insulating layers is laterally offset outward from a vertical plane including the outer sidewall of the blocking dielectric.

11. The three-dimensional memory device of claim 9 , further comprising a semiconductor material layer located in the substrate and comprising a single crystalline semiconductor material in epitaxial alignment with the epitaxial channel portion, wherein a vertical interface between the epitaxial channel portion and the semiconductor material layer is laterally offset outward from a vertical plane including the outer sidewall of the blocking dielectric.

12. The three-dimensional memory device of claim 9 , further comprising a silicon nitride plate contacting a portion of a sidewall of, and laterally surrounding the polycrystalline semiconductor channel, and overlying the epitaxial channel portion, and having a same composition and a same thickness as the silicon nitride spacers.

13. The three-dimensional memory device of claim 12 , further comprising a silicon oxide plate underlying the silicon nitride plate, and contacting a top surface of the epitaxial channel portion and laterally surrounding the polycrystalline semiconductor channel.

14. The three-dimensional memory device of claim 13 , further comprising annular silicon oxide spacers located at each level of the insulating layers, vertically spaced from one another, and contacting an outer sidewall of a respective silicon nitride spacer, wherein the silicon oxide plate has a same composition and a same thickness as the silicon oxide spacers.

15. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a vertical NAND device formed in a device region;
the electrically conductive layers comprise, or are electrically connected to a respective word line of the NAND device;
the device region comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;
the electrically conductive layers in the stack are in electrical contact with the plurality of control gate electrode and extend from the device region to a contact region including the plurality of electrically conductive via connections; and
the substrate comprises a silicon substrate containing a driver circuit for the NAND device.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Sel Jongsun
• Park Chan
• Suyama Atsushi
• Yu Frank
• Ogawa Hiroyuki
• Honma Ryoichi
• Yamaguchi Kensuke
• Iuchi Hiroaki
• Takeguchi Naoki
• Pham Tuan
• Sakakibara Kiyohiko
• Chen Jiao

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H01L27/11578

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic