Nonvolatile memory cell structure with assistant gate and memory array thereof

Patent metadata

Field	Value
Publication number	US-9601501-B2
Application number	US-201615155087-A
Country	US
Kind code	B2
Filing date	May 16, 2016
Priority date	Apr 2, 2014
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

An NVM array includes a plurality of NVM cells, a plurality of word lines extending along a first direction, a plurality of bit lines extending along a second direction, and a plurality of source lines. Each of the NVM cells includes a PMOS select transistor and a PMOS floating gate transistor serially connected to the PMOS select transistor. Each word line is electrically connected to the select gate of the PMOS select transistor. Each bit line is electrically connected to a doping region of the PMOS floating gate transistor of each of the plurality of NVM cells. Each source line is electrically connected to a doping region of the PMOS select transistor.

First claim

What is claimed is:

1. A non-volatile memory (NVM) array, comprising:
a plurality of NVM cells, wherein each of the NVM cells comprises:
a semiconductor substrate having therein a first N well;
a first oxide define (OD) region and a second oxide define (OD) region disposed within the semiconductor substrate;
a PMOS select transistor disposed on the first OD region, wherein the PMOS select transistor comprises a select gate, a first P + source doping region in the first N well, and a second P + doping region spaced apart from the first P + source doping region;
a PMOS floating gate transistor serially connected to the PMOS select transistor and being disposed over the first OD region, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region, the second P + doping region, and a third P + doping region spaced apart from the second P + source doping region, wherein the PMOS floating gate transistor serves as a charge storage element of the NVM cell;
an assistant gate protruding from the floating gate to one edge of the second OD region such that the assistant gate is capacitively coupled to the second OD region, wherein the assistant gate is formed integrally with the floating gate using a single layer of polysilicon;

a plurality of word lines extending along a first direction, wherein each of the word lines is electrically connected to the select gate of the PMOS select transistor of each of the plurality of NVM cells;
a plurality of bit lines extending along a second direction, wherein each of the bit lines is electrically connected to the third P + doping region of the PMOS floating gate transistor of each of the plurality of NVM cells; and
a plurality of source lines, wherein each of the source lines is electrically connected to the first P + doping region of the PMOS select transistor of each of the plurality of NVM cells.

2. The NVM array according to claim 1 , wherein the first OD region and the second OD region are disposed within the first N well.

3. The NVM array according to claim 1 , wherein an induced voltage coupled from the assistant gate is controlled by a bias of the first N well.

4. The NVM array according to claim 1 , wherein the first direction is perpendicular to the second direction.

5. The NVM array according to claim 1 , further comprising a P well and a third oxide define (OD) region within the semiconductor substrate.

6. The NVM array according to claim 5 , further comprising an erase gate extending continuously from the floating gate and traversing a junction between the first N well and the P well.

7. The NVM array according to claim 6 , wherein one distal end of the erase gate overlaps with the third OD region such that the erase gate is capacitively coupled to the third OD region.

8. The NVM array according to claim 5 , wherein the first OD region is disposed within the first N well, and the second OD region is disposed within the P well.

9. The NVM array according to claim 8 , further comprising a second N well, wherein third OD region is disposed within the second N well.

10. The NVM array according to claim 5 , wherein the first OD region and the second OD region are disposed within the first N well, and the third OD region is disposed within the P well.

11. The NVM array according to claim 5 , further comprising a plurality of erase lines for capacitively coupling an erase line voltage to the assistant gate of each of the plurality of NVM cells.

12. The NVM array according to claim 11 , wherein the erase lines extend along the first direction.

13. The NVM array according to claim 11 , wherein each of the erase lines is electrically connected to a doped region in the third OD region.

14. The NVM array according to claim 11 , wherein the erase lines, the bit lines, the source lines are formed in a metal interconnect scheme.

Assignees

• Ememory Technology Inc

Inventors

• Tsao Mu-Ying
• Chen Wei-Ren

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/491

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• G11C17/16 Primary

  using electrically-fusible links · CPC title

• G11C16/10

  Programming or data input circuits · CPC title