Antifuse OTP memory cell with performance improvement, and manufacturing method and operating method of memory

Patent metadata

Field	Value
Publication number	US-9324381-B2
Application number	US-201514606032-A
Country	US
Kind code	B2
Filing date	Jan 27, 2015
Priority date	Apr 2, 2014
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

An OTP memory cell including an antifuse unit and a select transistor is provided. The antifuse unit includes an antifuse layer and an antifuse gate disposed on a substrate in sequence, a modified extension doped region disposed in the substrate below the antifuse layer, and a first doped region and a second doped region disposed in the substrate at two opposite sides of the antifuse gate. The select transistor includes a select gate, a gate dielectric layer, a second doped region, and a third doped region. The select gate is disposed on the substrate. The gate dielectric layer is disposed between the select gate and the substrate. The second and the third doped region are respectively disposed in the substrate at two opposite sides of the select gate. The doped region, the antifuse layer and the antifuse gate form a varactor.

First claim

What is claimed is:

1. An antifuse one time programmable memory cell with performance improvement, comprising:
an antifuse unit, disposed on a substrate, wherein the substrate has a first conductive type, and the antifuse unit comprises:
an antifuse gate, disposed on the substrate;
an antifuse layer, disposed between the antifuse gate and the substrate;
a modified extension doped region, having a second conductive type, and disposed in the substrate below the antifuse layer, wherein the antifuse layer, the antifuse gate and the modified extension doped region form a varactor; and
a first doped region and a second doped region, having the second conductive type, and respectively disposed in the substrate at two opposite sides of the antifuse gate;

a select transistor, disposed on the substrate and comprising:
a select gate, disposed on the substrate;
a gate dielectric layer, disposed between the select gate and the substrate; and
the second doped region and a third doped region, having the second conductive type, and respectively disposed in the substrate at two opposite sides of the select gate.

2. The antifuse one time programmable memory cell with performance improvement as claimed in claim 1 , wherein a thickness of the antifuse layer is the same to a thickness of the gate dielectric layer.

3. The antifuse one time programmable memory cell with performance improvement as claimed in claim 1 , wherein the select transistor is a core metal oxide semiconductor transistor.

4. The antifuse one time programmable memory cell with performance improvement as claimed in claim 3 , wherein the select transistor further comprises:
a lightly doped region, having the second conductive type, and disposed between the select gate and the second doped region, wherein a junction depth of the lightly doped region is the same to a junction depth of the modified extension doped region, and a doping concentration of the lightly doped region is the same to a doping concentration of the modified extension doped region; and
a source/drain extension, having the second conductive type, and disposed between the select gate and the third doped region, wherein a junction depth of the source/drain extension is smaller than a junction depth of the modified extension doped region, and a doping concentration of the source/drain extension is greater than the doping concentration of the modified extension doped region.

5. The antifuse one time programmable memory cell with performance improvement as claimed in claim 1 , wherein the select transistor is an input/output metal oxide semiconductor transistor.

6. The antifuse one time programmable memory cell with performance improvement as claimed in claim 5 , wherein the select transistor further comprises:
a lightly doped region, having the second conductive type, and disposed between the select gate and the second doped region; and
a source/drain extension, having the second conductive type, and disposed between the select gate and the third doped region,
wherein junction depths of the lightly doped region, the source/drain extension and the modified extension doped region are the same, and doping concentrations of the lightly doped region, the source/drain extension and the modified extension doped region are the same.

7. The antifuse one time programmable memory cell with performance improvement as claimed in claim 1 , wherein the select transistor is a dual gate dielectric layer metal oxide semiconductor transistor, and a thickness of the gate dielectric layer close to the second doped region is greater than a thickness of the gate dielectric layer close to the third doped region.

8. The antifuse one time programmable memory cell with performance improvement as claimed in claim 7 , wherein the select transistor further comprises:
a lightly doped region, having the second conductive type, and disposed between the select gate and the second doped region, wherein a junction depth of the lightly doped region is the same to a junction depth of the modified extension doped region, and a doping concentration of the lightly doped region is the same to a doping concentration of the modified extension doped region; and
a source/drain extension, having the second conductive type, and disposed between the select gate and the third doped region, wherein a junction depth of the source/drain extension is smaller than a junction depth of the modified extension doped region, and a doping concentration of the source/drain extension is greater than the doping concentration of the modified extension doped region.

9. The antifuse one time programmable memory cell with performance improvement as claimed in claim 1 , wherein the first conductive type is one of a P-type and an N-type, and the second conductive type is another one of the P-type and the N-type.

10. The antifuse one time programmable memory cell with performance improvement as claimed in claim 1 , wherein the modified extension doped region is a well.

11. The antifuse one time programmable memory cell with performance improvement as claimed in claim 10 , wherein a part of the well extends to the bottom of the select gate.

12. The antifuse one time programmable memory cell with performance improvement as claimed in claim 11 , wherein the select transistor is a core metal oxide semiconductor transistor.

13. The antifuse one time programmable memory cell with performance improvement as claimed in claim 12 , wherein the select transistor further comprises:
a lightly doped region, having the second conductive type, and disposed between the select gate and the third doped region.

14. The antifuse one time programmable memory cell with performance improvement as claimed in claim 11 , wherein the select transistor is an input/output metal oxide semiconductor transistor.

15. The antifuse one time programmable memory cell with performance improvement as claimed in claim 14 , wherein the select transistor further comprises:
a lightly doped region, having the second conductive type, and disposed between the select gate and the third doped region.

16. The antifuse one time programmable memory cell with performance improvement as claimed in claim 10 , wherein a part of the well extends to the bottom of the second doped region.

17. The antifuse one time programmable memory cell with performance improvement as claimed in claim 16 , wherein the select transistor is a dual gate dielectric layer metal oxide semiconductor transistor, and a thickness of the gate dielectric layer close to the second doped region is greater than a thickness of the gate dielectric layer close to the third doped region.

18. The antifuse one time programmable memory cell with performance improvement as claimed in claim 17 , wherein the select transistor further comprises:
a lightly doped region, having the second conductive type, and disposed between the select gate and the second doped region; and
a source/drain extension, having the second conductive type, and disposed between the select gate and the third doped region, wherein a junction depth of the source/drain extension is smaller than a junction depth of the lightly doped region, and a doping concentration of the source/drain extension is greater than the doping concentration of the lightly doped region.

19. An operating method of a memory cell, the memory cell comprising a select transistor disposed on a substrate, and an antifuse unit connected to the select transistor in series, wherein the antifuse unit comprises an antifuse layer and an ant

Assignees

• Ememory Technology Inc

Inventors

• Wu Meng-Yi
• Chen Hsin-Ming
• Lu Chun-Hung

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/491

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title