Test structure for seal ring quality monitor

Patent metadata

Field	Value
Publication number	US-9601443-B2
Application number	US-70694007-A
Country	US
Kind code	B2
Filing date	Feb 13, 2007
Priority date	Feb 13, 2007
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A semiconductor structure includes a daisy chain adjacent to an edge of a semiconductor chip. The daisy chain includes a plurality of horizontal metal lines distributed in a plurality of metallization layers, wherein the horizontal metal lines are serially connected; a plurality of connecting pads in a same layer and electrically connecting the horizontal metal lines, wherein the connecting pads are physically separated from each other; and a plurality of vertical metal lines, each connecting one of the connecting pads to one of the horizontal metal lines, wherein one of the plurality of connecting pads is connected to one of the plurality of horizontal metal lines by only one of the plurality of vertical metal lines; and a seal ring adjacent and electrically disconnected from the daisy chain.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a daisy chain adjacent an edge of a semiconductor chip, the daisy chain comprising:
a plurality of horizontal metal lines distributed in a plurality of metallization layers, wherein the horizontal metal lines are serially connected;
a plurality of connecting pads in a same layer and electrically connecting the horizontal metal lines, wherein the plurality of connecting pads are physically separated from each other; and
a plurality of vertical metal lines, each connecting one of the plurality of connecting pads to one of the horizontal metal lines, wherein one of the plurality of connecting pads is connected to one of the plurality of horizontal metal lines by only one of the plurality of vertical metal lines;

a seal ring adjacent to and electrically disconnected from the daisy chain, wherein the seal ring comprises a side parallel to a respective side of the daisy chain, and wherein the seal ring is on an inner side of the daisy chain;
two bumps on the semiconductor chip, wherein the two bumps are in a region encircled by the seal ring; and
two metal lines, each being over and crossing the seal ring, wherein each of the two metal lines connects one of the two bumps to the daisy chain.

2. The semiconductor structure of claim 1 , wherein the plurality of connecting pads are not vertically overlapped.

3. The semiconductor structure of claim 1 , wherein the horizontal metal lines are not vertically overlapped.

4. The semiconductor structure of claim 1 , wherein the daisy chain comprises a plurality of test units, each comprising a bottom metal line and two electrical paths connected to opposite ends of the bottom metal line, with the bottom metal line being a bottom-most feature of the respective one of the plurality of test units, and wherein the bottom metal line of each of the plurality of test units is in a different metallization layer than the bottom metal lines in other ones of the plurality of test units.

5. The semiconductor structure of claim 4 , wherein in f the plurality of test units, the vertical metal lines are arranged in an order of lengths.

6. The semiconductor structure of claim 4 , wherein in the plurality of test units, the vertical metal lines are arranged in an alternating pattern according to lengths of the vertical metal lines.

7. The semiconductor structure of claim 4 , wherein all of the plurality of test units extends from a single one of the plurality of metallization layers downwardly.

8. The semiconductor structure of claim 1 , wherein the plurality of vertical metal lines each comprises a plurality of metal pads, each in one of the metallization layers, and a plurality of vias connecting the metal pads.

9. The semiconductor structure of claim 1 , wherein the daisy chain extends along all edges of the semiconductor chip, and wherein a length of each side of the daisy chain is substantially close to a length of a respective side of the seal ring, with the respective side of the seal ring parallel to the each side of the daisy chain.

10. The semiconductor structure of claim 9 , wherein the daisy chain forms a closed loop, and is disconnected from the seal ring.

11. A semiconductor structure comprising:
a semiconductor chip comprising a semiconductor substrate; and
a test structure comprising a plurality of serially connected test units, each comprising:
a first top metal pad and a second top metal pad, wherein all first top metal pads and all second top metal pads of the plurality of serially connected test units are in a single metallization layer;
a bottom metal line, wherein the bottom metal line of each of the plurality of serially connected test units is in a different metallization layer than the bottom metal lines in all other ones of the plurality of serially connected test units, and the bottom metal line is a bottom-most feature of a respective one of the plurality of serially connected test units;
a first vertical electrical path connecting the first top metal pad to a first end of the bottom metal line; and
a second vertical electrical path connecting the second top metal pad to a second end of the bottom metal line;

two bumps on the semiconductor chip and electrically connected to the test structure; and
a seal ring adjacent to the test structure, wherein the test structure comprises a side having a length substantially equal to or greater than a length of a side of the seal ring, and wherein the test structure comprises a portion between the seal ring and an edge of the semiconductor chip.

12. The semiconductor structure of claim 11 further comprising a sacrificial seal ring between the portion of the test structure and the edge.

13. The semiconductor structure of claim 11 further comprising two additional bumps on the semiconductor chip, wherein the two bumps and the two additional bumps are corner bumps, each at a corner of the semiconductor chip.

14. The semiconductor structure of claim 11 , wherein the test structure comprises two sides, each parallel to a side of the seal ring, and wherein each of the sides of the test structure has a length substantially equal to a length of a respectively side of the seal ring.

15. The semiconductor structure of claim 11 , wherein the second top metal pad of a first one of the plurality of serially connected test units is joined with the first top metal pad of a second one of the plurality of serially connected test units to form an integrated metal pad.

16. A semiconductor chip comprising:
a test structure extending along at least one edge of the semiconductor chip, the test structure comprising a plurality of test units, each comprising:
a first bottom metal pad and a second bottom metal pad, wherein all first bottom top metal pads and all second bottom metal pads of the plurality of serially connected test units are in a single metallization layer;
a top metal line, wherein the top metal line of each of the plurality of test units is in a different metallization layer than the top metal lines in all other ones of the plurality of test units, and the top metal line is a top-most feature of a respective one of the plurality of test units;
a first vertical electrical path connecting the first bottom metal pad to a first end of the top metal line; and
a second vertical electrical path connecting the second bottom metal pad to a second end of the top metal line;

two bumps on the semiconductor chip, wherein the plurality of test units is connected in series between the two bumps; and
a seal ring adjacent to the test structure.

17. The semiconductor chip of claim 16 , wherein the two bumps are corner bumps.

18. The semiconductor chip of claim 16 , wherein the test structure comprises a side parallel to a side of the seal ring.

19. The semiconductor chip of claim 16 , wherein the test structure comprises a closed loop.

20. The semiconductor chip of claim 16 , wherein the second bottom metal pad of a first one of the plurality of test units is joined with the first bottom metal pad of a second one of the plurality of test units to form an integrated metal pad.

Assignees

• Tsai Hao-Yi
• Hsu Shih-Hsun
• Chang Shih-Cheng
• Hou Shang-Yun
• Chen Hsien-Wei
• Tsai Chia-Lun
• Liu Benson
• Jeng Shin-Puu
• Wu Anbiarshy
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Hao-Yi
• Hsu Shih-Hsun
• Chang Shih-Cheng
• Hou Shang-Yun
• Chen Hsien-Wei
• Tsai Chia-Lun
• Liu Benson
• Jeng Shin-Puu
• Wu Anbiarshy

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10W72/5525

  comprising copper [Cu] · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/922

  Bond pads being integral with underlying chip-level interconnections · CPC title