Semiconductor structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9601439-B1
Application number	US-201514840808-A
Country	US
Kind code	B1
Filing date	Aug 31, 2015
Priority date	Aug 31, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A semiconductor structure includes a substrate, a die disposed over the substrate, and including a die pad disposed over the die and a seal ring disposed at a periphery of the die and electrically connected with the die pad, a polymeric layer disposed over the die, a via extending through the polymeric layer and electrically connected with the die pad, and a molding disposed over the substrate and surrounding the die and the polymeric layer, wherein the seal ring is configured for grounding.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate;
a die disposed over the substrate, and including
a die pad disposed over the die and
a seal ring embeddedly arranged within the die at an upper periphery region thereof and electrically connected with the die pad;

a polymeric layer disposed over the die;
a via extending through the polymeric layer and electrically connected with the die pad; and
a molding disposed over the substrate and surrounding the die and the polymeric layer,
wherein the seal ring is configured for grounding.

2. The semiconductor structure of claim 1 , wherein the seal ring extends along the periphery of the die to at least partially enclose a central portion of the die.

3. The semiconductor structure of claim 1 , wherein the seal ring is connectable to ground.

4. The semiconductor structure of claim 1 , wherein the via is disposed over the die pad and surrounded by the polymeric layer.

5. The semiconductor structure of claim 1 , further comprising a redistribution layer (RDL) disposed over the die and the molding and including an interconnect structure electrically connecting with the via, the die pad and the seal ring.

6. The semiconductor structure of claim 5 , wherein the interconnect structure of the RDL is configured for grounding or is connectable to ground.

7. A semiconductor structure, comprising:
a first redistribution layer (RDL) including a first interconnect structure;
a dielectric layer disposed over the first RDL;
a via electrically connected with the first interconnect structure and extending through the dielectric layer;
a second redistribution layer (RDL) disposed over the dielectric layer and the via, and including a second interconnect structure electrically connected with the first interconnect structure by the via;
a die disposed over the second RDL; and
a source electrically connected with the die, configured to emit an electromagnetic radiation, at least partially disposed within the die and disposed between the die and the first RDL,

wherein the first interconnect structure of the first RDL and the second interconnect structure of the second RDL are configured to absorb the electromagnetic radiation of a predetermined frequency.

8. The semiconductor structure of claim 7 , wherein the first interconnect structure surrounds a first portion of the source, or the second interconnect structure partially surrounds a second portion of the source.

9. The semiconductor structure of claim 7 , wherein the via extends between the first RDL and the second RDL and electrically connects the first interconnect structure with the second interconnect structure.

10. The semiconductor structure of claim 7 , wherein the second interconnect structure is in a C shape, or the first interconnect structure is in an annular or a closed loop shape.

11. The semiconductor structure of claim 7 , wherein the source extends from the die to the first RDL or the second RDL.

12. The semiconductor structure of claim 7 , wherein the first interconnect structure and the second interconnect structure are aligned and disposed opposite to each other.

13. The semiconductor structure of claim 7 , wherein the first interconnect structure and the second interconnect structure are configured in substantially same dimension and shape.

14. The semiconductor structure of claim 7 , further comprising a molding disposed over the second RDL and covering the die.

15. A method of manufacturing a semiconductor structure, comprising:
receiving a substrate;
disposing a die over the substrate, wherein the die includes a die pad disposed over the substrate and a seal ring embeddedly arranged within the die at an upper periphery region thereof and electrically connected with the die pad;
forming a via over the die pad of the die;
disposing a polymeric layer over the die;
disposing a molding over the substrate and surrounding the die and the polymeric layer,

wherein the seal ring is configured for grounding.

16. The method of claim 15 , wherein the seal ring is electrically connected with the via through the die pad.

17. The method of claim 15 , wherein the via and the die pad are electrically grounded by grounding the seal ring.

18. The method of claim 15 , wherein forming the via includes disposing a conductive material over the die pad.

19. The method of claim 15 , further comprising:
forming a redistribution layer (RDL) over the polymeric layer, wherein the RDL includes an interconnect structure disposed within the RDL, electrically connected with the via, the die pad and the seal ring, and configured for grounding.

20. The method of claim 19 , wherein the interconnect structure of the RDL extends along the periphery of the die or extends over a central portion of the die.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tang Tzu-Chun
• Chang Shou Zen
• Chen Wei-Ting
• Lin In-Tsang
• Chen Vincent
• Wang Chuei-Tang
• Wu Kai-Chiang
• Lu Chun-Lin

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title