Semiconductor package with embedded components and method of making the same

Patent metadata

Field	Value
Publication number	US-9601435-B2
Application number	US-201514603166-A
Country	US
Kind code	B2
Filing date	Jan 22, 2015
Priority date	Jan 22, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A semiconductor package may include a lower substrate with one or more electronic components attached to a surface thereof and an upper substrate with one or more cavities wherein the upper substrate is attached to the lower substrate at a plurality of connection points with the one or more electronic components fitting within a single cavity or a separate cavity for each component that allow the overall form factor of the semiconductor package to remain smaller. The plurality of connection points provide a mechanical and electrical connection between the upper and lower substrate and may include solder joints there between as well as conductive filler particles that create an adhesive reinforcement matrix when compressed for assembly.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a first electronic component mounted on a lower substrate layer;
a second electronic component mounted on the lower substrate layer adjacent the first electronic component;
an adhesive layer on a surface of the first electronic component and a surface of the second electronic component;
an upper substrate layer having a cavity therein, the upper substrate layer attached to the lower substrate layer such that the first electronic component and the second electronic component are located within the cavity, wherein the adhesive layer is on a surface of the lower substrate layer and extends between the lower substrate layer and the upper substrate layer; and
a plurality of connection points located between the upper substrate layer and the lower substrate layer, the plurality of connection points electrically and mechanically connecting the upper substrate layer and the lower substrate layer.

2. The semiconductor package of claim 1 , wherein the first electronic component is one of a semiconductor die, a memory, or an integrated circuit and wherein the second electronic component is one of a semiconductor die, a memory, or an integrated circuit.

3. The semiconductor package of claim 1 , wherein the plurality of connection points include a solder material.

4. The semiconductor package of claim 1 , further comprising an anisotropic conductive adhesive between the plurality of connection points, the anisotropic conductive adhesive containing conductive filler particles.

5. The semiconductor package of claim 4 , wherein the conductive filler particles comprises one of copper, silver, gold, or alloys of the same.

6. The semiconductor package of claim 5 , further comprising a plurality of upper substrate layer interconnections in the upper substrate layer and a plurality of lower substrate layer interconnections in the lower substrate layer.

7. The semiconductor package of claim 1 , wherein the semiconductor package is integrated into one of a mobile phone, a mobile communication device, a pager, a personal digital assistant, a personal information manager, a mobile hand-held computer, a laptop computer, a wireless device, or a wireless modem.

8. A semiconductor package, comprising:
a first electronic component mounted on a lower substrate layer;
a second electronic component mounted on the lower substrate layer adjacent the first electronic component;
an adhesive layer on a surface of the first electronic component and a surface of the second electronic component;
an upper substrate layer having a first cavity and a second cavity, the upper substrate layer attached to the lower substrate layer such that the first electronic component is located in the first cavity and the second electronic component is located in the second cavity, wherein the adhesive layer is on a surface of the lower substrate layer and extends between the lower substrate layer and the upper substrate layer; and
a plurality of connection points located between the upper substrate layer and the lower substrate layer, the plurality of connection points electrically and mechanically connecting the upper substrate layer and the lower substrate layer.

9. The semiconductor package of claim 8 , wherein the first electronic component is one of a semiconductor die, a memory, or an integrated circuit and wherein the second electronic component is one of a semiconductor die, a memory, or an integrated circuit.

10. The semiconductor package of claim 8 , wherein the plurality of connection points include a solder material.

11. The semiconductor package of claim 8 , wherein the adhesive layer comprises an anisotropic conductive adhesive containing conductive filler particles.

12. The semiconductor package of claim 11 , wherein the conductive filler particles comprises one of copper, silver, gold, or alloys of the same.

13. The semiconductor package of claim 12 , further comprising a plurality of upper substrate layer interconnections in the upper substrate layer and a plurality of lower substrate layer interconnections in the lower substrate layer.

14. The semiconductor package of claim 13 , wherein the semiconductor package is integrated into one of a mobile phone, a mobile communication device, a pager, a personal digital assistant, a personal information manager, a mobile hand-held computer, a laptop computer, a wireless device, or a wireless modem.

Assignees

• Qualcomm Inc

Inventors

• Kim Chin-Kwan
• Rae David Fraser
• Kumar Rajneesh
• Shah Milind Pravin
• Bchir Omar James

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07354

  changes in dispositions · CPC title

• H10W72/07338

  hardening the adhesive by curing, e.g. thermosetting · CPC title