Interposer and methods of forming and testing an interposer

Patent metadata

Field	Value
Publication number	US-9601424-B2
Application number	US-201514684664-A
Country	US
Kind code	B2
Filing date	Apr 13, 2015
Priority date	Apr 13, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A method of forming and testing an interposer includes forming vias in a semiconductor material of a wafer having a front side and a back side. The method further includes disposing an electrically conductive layer on the front side of the wafer such that the layer is electrically connected to the vias. The method also includes forming electrically conductive pads on the front side of the wafer, wherein each electrically conductive pad is electrically connected to the electrically conductive layer. The method further includes forming electrically conductive bumps on the back side of the wafer, wherein each electrically conductive bump is electrically connected to at least one via. The method also includes testing electrical connectivity from a first bump to a second bump of the electrically conductive bumps.

First claim

What is claimed is:

1. A method of forming and testing an interposer, comprising:
forming vias in a semiconductor material of a wafer having a front side and a back side;
disposing an electrically conductive layer on the front side of the wafer such that the electrically conductive layer is electrically connected to the vias;
forming electrically conductive pads on the front side of the wafer wherein each electrically conductive pad is electrically connected to the electrically conductive layer and wherein the electrically conductive layer is sandwiched between at least one of the conductive pads and at least one of the vias;
forming electrically conductive bumps on the back side of the wafer wherein each electrically conductive bump is electrically connected to at least one via; and
testing electrical connectivity from a first bump of the electrically conductive bumps to a second bump of the electrically conductive bumps after said disposing of the electrically conductive layer.

2. The method as set forth in claim 1 , further comprising selectively etching the electrically conductive layer such that a first plurality of electrically conductive pads are electrically connected together and electrically isolated from a second plurality of electrically conductive pads.

3. The method as set forth in claim 2 , wherein testing electrical connectivity from the first bump to the second bump is performed after said selectively etching the layer.

4. The method as set forth in claim 1 , further comprising reporting a result of said testing electrical connectivity to a user.

5. The method as set forth in claim 1 , further comprising removing a portion of the back side of the wafer to expose the vias after said disposing an electrically conductive layer and prior to said forming electrically conductive bumps.

6. The method as set forth in claim 1 , wherein said testing electrically connectivity comprises:
electrically connecting a first probe to the first bump;
electrically connecting a second probe to the second bump;
applying an electric current to the first probe; and
sensing the electric current received by the second probe.

7. The method as set forth in claim 1 , further comprising bonding the front side of the wafer to a carrier.

8. The method as set forth in claim 7 , wherein said testing electrical connectivity from a first bump of the electrically conductive bumps to a second bump of the electrically conductive bumps occurs after said bonding of the front side of the wafer to the carrier.

9. An interposer for an integrated circuit, comprising:
a wafer comprising a semiconductor material and defining a front side and a back side;
vias disposed within said semiconductor material;
an electrically conductive layer disposed on said front side and electrically connected to said vias;
electrically conductive pads disposed on said front side of said wafer and electrically connected to said electrically conductive layer wherein said electrically conductive layer is sandwiched between at least one of said conductive pads and at least one of said vias; and
electrically conductive bumps disposed on said back side of said wafer wherein each electrically conductive bump is electrically connected to at least one of said vias.

10. The interposer as set forth in claim 9 wherein said front side is bonded to a carrier.

11. The interposer as set forth in claim 10 wherein said electrically conductive layer is selectively etched such that a first plurality of said electrically conductive pads is electrically connected together and a second plurality of said electrically conductive pads is electrically connected together.

12. The interposer as set forth in claim 11 wherein said first plurality and said second plurality of said electrically conductive pads are electrically isolated from one another.

13. The interposer as set forth in claim 9 wherein said electrically conductive layer is selectively etched such that a first plurality of said electrically conductive pads is electrically connected together and a second plurality of said electrically conductive pads is electrically connected together.

14. The interposer as set forth in claim 13 wherein said first plurality and said second plurality of said electrically conductive pads are electrically isolated from one another.

Assignees

• Globalfoundries Inc

Inventors

• Agarwal Rahul
• Oswald Jens
• Lu Sheng Feng
• Tan Soon Leng
• Lam Jeffrey

Classifications

• G01R31/52

  Testing for short-circuits, leakage current or ground faults · CPC title

• G01R31/2831

  Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates (G01R31/318511 takes precedence; testing during manufacture H10P74/00) · CPC title

• H10P72/7436

  used to support a device or a wafer when forming electrical connections thereto · CPC title

• H10P72/7422

  used to protect an active side of a device or wafer · CPC title

• H10P72/7416

  used during dicing or grinding · CPC title