Under die surface mounted electrical elements

Patent metadata

Field	Value
Publication number	US-9601423-B1
Application number	US-201514974484-A
Country	US
Kind code	B1
Filing date	Dec 18, 2015
Priority date	Dec 18, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A laminate includes a buildup layer having a top and a bottom and a solder mask contacting the top. The laminate also includes a circuit element disposed on the top of the buildup layer and at least partially covered by the solder mask, the circuit element including a first via formed therein that allows for a power signal provided to an underside of the circuit element to be provided to a first connection on a top of the circuit element.

First claim

What is claimed is:

1. A laminate comprising:
a buildup layer having a top and a bottom;
a solder mask contacting the top; and
a circuit element disposed directly on the top of the buildup layer and at least partially covered by the solder mask, the circuit element including a first via formed therein that allows for a power signal provided to an underside of the circuit element to be provided to a first connection on a top of the circuit element;
wherein the circuit element is one of: a metal-insulator-metal capacitor, a resistor, an inductor, or a voltage regulator.

2. The laminate of claim 1 , wherein the circuit element further includes a second via that allows for a power signal provided to a second connection on the top of the second circuit element to be provided to the underside of the circuit element.

3. The laminate of claim 1 , further comprising:
a positive solder ball; and
a positive via connecting the positive solder ball to the first via through the buildup layer.

4. The laminate of claim 1 , wherein the circuit element further includes:
a second connection on the top of the circuit element; and
a second via that allows for a signal provided to the second connection to be provided to the underside of the circuit element;
and wherein the laminate further includes:
a negative solder ball; and
a negative via connecting negative solder ball to the second via through the buildup layer.

5. The laminate of claim 4 , further comprising:
a third connection electrically coupled to the first connection by a connecting path formed within the element;
wherein the first connection is in electrical communication with a first integrated circuit (IC) and the third connection is in electrical communication with a second IC.

6. The laminate of claim 1 , further comprising:
a core;
wherein the bottom contacts the core.

7. A module comprising:
a laminate comprising:
a buildup layer having a top and a bottom;
a solder mask contacting the top; and
a circuit element disposed directly on the top of the buildup layer and at least partially covered by the solder mask, the circuit element including a first via formed therein that allows for a power signal provided to an underside of the circuit element to be provided to a first connection on a top of the circuit element, wherein the circuit element is one of: a metal-insulator-metal capacitor, a resistor, an inductor, or a voltage regulator; and

a die disposed over the laminate and in electrical communication with the circuit element.

8. The module of claim 7 , wherein the circuit element is disposed entirely beneath the die.

9. The module of claim 6 , further comprising:
solder balls connecting the die to the circuit element.

10. The module of claim 7 , wherein the circuit element further includes a second via that allows for a power signal provided to a second connection on the top of the second circuit element to be provided to the underside of the circuit element.

11. The module of claim 7 , further comprising:
a positive solder ball; and
a positive via connecting the positive solder ball to the first via through the buildup layer.

12. The module of claim 7 , wherein the circuit element further includes:
a second connection on the top of the circuit element; and
a second via that allows for a signal provided to the second connection to be provided to the underside of the circuit element;
and wherein the laminate further includes:
a negative solder ball; and
a negative via connecting positive solder ball to the second via through the buildup layer.

13. The module of claim 12 , further comprising:
a third connection electrically coupled to the first connection by a connecting path formed within the element;
wherein the first connection in electrical communication with a first integrated circuit (IC) within the die and the third connection is in electrical communication with a second IC within the die.

14. The module of claim 7 , wherein the laminate further includes:
a core;
wherein the bottom contacts the core.

15. A method of forming a laminate comprising:
forming a buildup layer having a top and a bottom;
disposing a circuit element directly on the top of the buildup layer, the circuit element including a first via formed therein that allows for a power signal provided to an underside of the circuit element to be provided to a first connection on a top of the circuit element; and
forming a solder mask over at least a portion of the circuit element and the top;
wherein the circuit element is one of: a metal-insulator-metal capacitor, a resistor, an inductor, or a voltage regulator.

Assignees

• IBM

Inventors

• Arvin Charles L
• Casey Jon A
• Erwin Brian M
• Ostrander Steven P
• Quinlan Brian W

Classifications

• H10W90/728

  between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title