Method for preventing die pad delamination

Patent metadata

Field	Value
Publication number	US-9601414-B2
Application number	US-201514968234-A
Country	US
Kind code	B2
Filing date	Dec 14, 2015
Priority date	Dec 17, 2014
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

The invention is directed to a method for inhibiting or preventing delamination at the interface of the die attach/mold compound and the die pad of a semiconductor device and a semiconductor device formed by such method. The method includes providing a leadframe having a top surface; coating the top surface of the leadframe with first and second silane coating; heating the silane coatings to form a porous layer having a porosity of at least 10%; applying a die to the porous layer; securing the die to the porous layer by a die attaching compound; and after the curing of die attach material and wire bonding, a mold compound is applied through molding.

First claim

What is claimed:

1. A method for inhibiting or preventing delamination at the interface of the die attach/mold compound and the die pad of a semiconductor device comprising:
providing a leadframe having a first surface;
applying a first silane on said first surface of said leadframe to form a first coating layer, said first silane includes at least one functional group selected from a sulfur functional group, a nitrogen functional group, and a phosphorus functional group;
applying a second silane to said first coating layer to form a second coating layer, said second silane formed of one or more different compounds from said first silane;
heating said first and second coating layers to form a porous layer having a porosity of at least 10%;
applying a die to said porous layer;
at least partially securing said die to said porous layer by a die attaching compound; and
applying a mold compound at least partially over the said die and said leadframe.

2. The method as defined in claim 1 , wherein a boiling point of said first silane is at least 130° C.

3. The method as defined in claim 1 , wherein said step of heating includes heating said first and second coatings for at least 1 minute at a temperature of at least 60° C. until said porosity of said porous layer is between 10-60%.

4. The method as defined in claim 2 , wherein said step of heating includes heating said first and second coatings for at least 1 minute at a temperature of at least 60° C. until said porosity of said porous layer is between 10-60%.

5. The method as defined in claim 1 , wherein said first silane includes one or more compounds selected from the group consisting of bis[3-(triethoxysilyl)propyl]-tetrasulfide, 2-(Diphenylphosphino) ethyltriethoxysilane, (Aminoethylaminomethyl) phenethyltrimethoxysilane, and 3-Aminopropyltriethoxysilane.

6. The method as defined in claim 4 , wherein said first silane includes one or more compounds selected from the group consisting of bis[3-(triethoxysilyl)propyl]-tetrasulfide, 2-(Diphenylphosphino) ethyltriethoxysilane, (Aminoethylaminomethyl) phenethyltrimethoxysilane, and 3-Aminopropyltriethoxysilane.

7. The method as defined in claim 1 , wherein said second silane includes one or more compounds selected from the group consisting of 3-Aminopropyltrimethoxysilane, 3-Glycidyloxypropyl) trimethoxysilane, diethylaminotrimethylsilane, siloxanes, vinyltrimethoxysilane, gamma-Aminopropyl triethoxysilane, methacryloxypropyl trimethoxysilane, glycidoxypropyl trimethoxysilane, and triethoxyoctylsilane.

8. The method as defined in claim 6 , wherein said second silane includes one or more compounds selected from the group consisting of 3-Aminopropyltrimethoxysilane, 3-Glycidyloxypropyl) trimethoxysilane, diethylaminotrimethylsilane, siloxanes, vinyltrimethoxysilane, gamma-Aminopropyl triethoxysilane, methacryloxypropyl trimethoxysilane, glycidoxypropyl trimethoxysilane, and triethoxyoctylsilane.

9. The method as defined in claim 1 , wherein said leadframe includes a metal selected from the group consisting of gold, silver, copper, nickel and palladium, said porous layer forming one or more chemical bonds with said leadframe selected from the group consisting of an Au—S chemical bond, an Au—P chemical bond, an Au—N chemical bond, a Cu—S chemical bond, a Cu—P chemical bond, a Cu—N chemical bond, an Ag—S chemical bond, an Ag—P chemical bond, an Ag—N chemical bond, a Ni—S chemical bond, a Ni—P chemical bond, a Ni—N chemical bond, a Pd—S chemical bond, a Pd—P chemical bond and a Pd—N chemical bond.

10. The method as defined in claim 8 , wherein said leadframe includes a metal selected from the group consisting of gold, silver, copper, nickel and palladium, said porous layer forming one or more chemical bonds with said leadframe selected from the group consisting of an Au—S chemical bond, an Au—P chemical bond, an Au—N chemical bond, a Cu—S chemical bond, a Cu—P chemical bond, a Cu—N chemical bond, an Ag—S chemical bond, an Ag—P chemical bond, an Ag—N chemical bond, a Ni—S chemical bond, a Ni—P chemical bond, a Ni—N chemical bond, a Pd—S chemical bond, a Pd—P chemical bond and a Pd—N chemical bond.

11. The method as defined in claim 1 , further including the steps of a) at least partially curing said die attaching compound, b) performing a wire bonding process on said die, and c) using a molding process to apply said mold compound over said die and said die attaching compound, said die and said die attaching compound at least partially encapsulated or fully encapsulated between said mold compound and said porous layer, said leadframe, or combinations thereof.

12. The method as defined in claim 11 , further including the step of curing said mold compound.

13. The method as defined in claim 1 , wherein said porous layer has a thickness between 2-20 μm.

14. A semiconductor device comprising a leadframe, a die, a porous layer and a die attaching compound, wires, mold compound, said porous layer positioned in a first surface of said leadframe and having a chemical bond with said leadframe, said chemical bond including one or more bonds formed by an element selected from the group consisting of nitrogen, sulfur and phosphorous, said porous layer having a porosity of at least 10%, said die connected to said porous layer by said die attaching compound, said die attaching compound having a different formulation from said porous layer.

15. The semiconductor device as defined in claim 14 , wherein said porous layer includes first and second silanes that have been exposed to heat, said first silane includes at least one functional group selected from a sulfur functional group, a nitrogen functional group, and a phosphorus functional group, said second silane includes at least one functional group selected from amines, epoxide and vinyl in a second layer.

16. The semiconductor device as defined in claim 15 , wherein said first silane includes a compound selected from the group consisting of bis[3-(triethoxysilyl)propyl]-tetrasulfide, 2-(Diphenylphosphino) ethyltriethoxysilane, (Aminoethylaminomethyl) phenethyltrimethoxysilane, and 3-Aminopropyltriethoxysilane, said second silane includes a compound selected from the group consisting of 3-Glycidyloxypropyl) trimethoxysilane, diethylaminotrimethyl silane, siloxanes, vinyltrimethoxysilane, gamma-Aminopropyl triethoxysilane, methacryloxypropyl trimethoxysilane, glycidoxypropyl trimethoxysilane, and triethoxyoctylsilane.

17. The semiconductor device as defined in claim 14 , wherein said leadframe includes a metal selected from the group consisting of gold, silver, copper, nickel and palladium, said one or more chemical bonds between said porous layer and said leadframe selected from the group consisting of an Au—S chemical bond, an Au—P chemical bond, an Au—N chemical bond, a Cu—S chemical bond, a Cu—P chemical bond, a Cu—N chemical bond, an Ag—S chemical bond, an Ag—P chemical bond, an Ag—N chemical bond, a Ni—S chemical bond, a Ni—P chemical bond, a Ni—N chemical bond, a Pd—S chemical bond, a Pd—P chemical bond and a Pd—N chemical bond.

18. The semiconductor device as defined in claim 14 , wherein said die and said die attaching compound are at least partially encapsulated or fully encapsulated between a mold compound and said porous layer, said leadframe, or combinations thereof.

19. The semiconductor device as defined in claim 14 , wherein said porous layer has an average a thickness of between 2-20 μm.

Assignees

• Texas Instruments Inc

Inventors

• Zhang Rongwei
• Castro Abram

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W72/07341

  Controlling the bonding environment, e.g. atmosphere composition or temperature · CPC title

• H10W72/07338

  hardening the adhesive by curing, e.g. thermosetting · CPC title