Electronic package and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-9601403-B2
Application number	US-201514982276-A
Country	US
Kind code	B2
Filing date	Dec 29, 2015
Priority date	Aug 14, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

An electronic package is provided, which includes: a first circuit structure; at least first electronic element disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; a first encapsulant encapsulating the first electronic element and the first conductive element; and a second circuit structure formed on the first encapsulant and electrically connected to the first conductive element. By directly disposing the electronic element having high I/O functionality on the circuit structure, the invention eliminates the need of a packaging substrate having a core layer and thus reduces the thickness of the electronic package. The invention further provides a method for fabricating the electronic package.

First claim

What is claimed is:

1. An electronic package, comprising:
a first circuit structure having a first surface and a second surface opposite to the first surface;
at least a first electronic element disposed on the first surface of the first circuit structure;
a first encapsulant formed on the first surface of the first circuit structure to encapsulate the first electronic element;
at least a first conductive element formed on the first surface of the first circuit structure and embedded in and exposed from the first encapsulant; and
a second circuit structure formed on the first encapsulant and electrically connected to the first conductive element.

2. The package of claim 1 , wherein the first encapsulant encapsulates the first conductive element.

3. The package of claim 1 , wherein an opening is formed in the first encapsulant to expose a portion of the first surface of the first circuit structure, and a third electronic element is disposed on the exposed portion of the first circuit structure.

4. The package of claim 3 , wherein the third electronic element is electrically connected to the second circuit structure.

5. The package of claim 1 , wherein an opening is formed in the first encapsulant to expose a portion of the first surface of the first circuit structure, the first conductive element being received in the opening and connected to the second circuit structure.

6. The package of claim 5 , further comprising a second encapsulant formed in the opening to encapsulate the first conductive element.

7. The package of claim 1 , further comprising at least a second electronic element disposed on the first encapsulant and electrically connected to the second circuit structure.

8. The package of claim 7 , further comprising a second encapsulant formed on the first encapsulant for encapsulating the second electronic element.

9. The package of claim 7 , further comprising a fourth electronic element bonded to the second electronic element.

10. The package of claim 1 , further comprising a plurality of second conductive elements formed on the second surface of the first circuit structure.

11. A method for fabricating an electronic package, comprising the steps of:
providing a first circuit structure having opposite first and second surfaces;
forming at least a first conductive element on the first surface of the first circuit structure and disposing at least a first electronic element on the first surface of the first circuit structure;
forming a first encapsulant on the first surface of the first circuit structure to encapsulate the first electronic element and the first conductive element, wherein the first conductive element is exposed from the first encapsulant;
forming a second circuit structure on the first encapsulant, wherein the second circuit structure is electrically connected to the first conductive element; and
disposing at least a second electronic element on the first encapsulant, wherein the second electronic element is electrically connected to the second circuit structure.

12. The method of claim 11 , further comprising forming a second encapsulant on the first encapsulant to encapsulate the second electronic element.

13. The method of claim 11 , further comprising forming a plurality of second conductive elements on the second surface of the first circuit structure.

14. A method for fabricating an electronic package, comprising the steps of:
providing a first circuit structure having opposite first and second surfaces;
disposing at least a first electronic element on the first surface of the first circuit structure;
forming a first encapsulant on the first surface of the first circuit structure to encapsulate the first electronic element, wherein the first encapsulant has at least an opening exposing a portion of the first surface of the first circuit structure;
forming a second circuit structure on the first encapsulant;
disposing at least a second electronic element on the first encapsulant, wherein the second electronic element is electrically connected to the second circuit structure; and
forming a plurality of first conductive elements on the second circuit structure and the portion of the first circuit structure exposed from the opening of the first encapsulant.

15. The method of claim 14 , wherein the number of the opening in the first encapsulant is more than one, at least a third electronic element being received in one of the openings and the first conductive elements being received in the other openings.

16. The method of claim 15 , wherein the third electronic element is electrically connected to the second electronic element or the second circuit structure.

17. The method of claim 14 , further comprising forming a second encapsulant on the first encapsulant and in the opening to encapsulate the second electronic element and the first conductive elements.

18. The method of claim 17 , wherein the second encapsulant has at least an opening, the second electronic element being partially exposed from the opening for bonding with a fourth electronic element.

19. The method of claim 14 , further comprising forming a plurality of second conductive elements on the second surface of the first circuit structure.

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Chen Lu-Yi
• Ma Guang-Hwa
• Chen Shih-Ching
• Lu Chang-Lun

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title