Semiconductor device and method of manufacturing a semiconductor device having a glass piece and a single-crystalline semiconductor portion

US9601376B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9601376-B2
Application numberUS-201514960505-A
CountryUS
Kind codeB2
Filing dateDec 7, 2015
Priority dateMar 8, 2012
Publication dateMar 21, 2017
Grant dateMar 21, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes a glass piece and an active semiconductor element formed in a single-crystalline semiconductor portion. The single-crystalline semiconductor portion has a working surface, a rear side surface opposite to the working surface and an edge surface connecting the working and rear side surfaces. The glass piece has a portion extending along and in direct contact with the edge surface of the single-crystalline semiconductor portion.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of manufacturing a semiconductor device, the method comprising: forming semiconductor elements in semiconductor portions of a semiconductor substrate, forming a cavity in a working surface of the semiconductor substrate, wherein the cavity forms a grid separating the semiconductor portions comprising the semiconductor elements; arranging a glass material in contact with the working surface of the substrate, wherein the glass material comprises at least one of a powder, glass frits and pellets or is a glass disk; pressing the glass material and the semiconductor substrate against each other, wherein a temperature of the glass material and a force exerted on the glass material are controlled such that fluidified glass material flows into the cavity; controlling the temperature and the force to re-solidify the fluidified glass material, the re-solidified glass material forming a glass piece with a protrusion extending into the cavity, wherein the glass piece is in-situ bonded to the semiconductor substrate; and separating the semiconductor substrate along the cavity to obtain a plurality of semiconductor dies from the semiconductor substrate such that the glass material forms glass frames encompassing the semiconductor dies. 2. The method of claim 1 , wherein the glass material has a glass transition and the glass material fluidifies when the temperature of the glass material exceeds a glass transition temperature. 3. The method of claim 1 , wherein the glass material is an inorganic glass selected from the group consisting of soda-lime glass, undoped silica glass, silica glass doped with at least one dopant, a photostructurable glass, and a polymer selected from the group consisting of polynorbornene, polystyrene, polycarbonate, polyimide, and benzocyclobutene, and wherein the at least one dopant is selected from the group consisting of boron, sodium, calcium, potassium and aluminum. 4. The method of claim 1 , further comprising removing excess portions of the glass piece outside the cavity using an etch process that removes the glass material selectively against the substrate. 5. The method of claim 1 , further comprising forming, before the bonding, at least one auxiliary layer lining the cavity, the at least one auxiliary layer forming at least one of an electric passivation layer lining the cavity, a moisture passivation layer lining the cavity, a getter layer lining the cavity, the getter layer being adapted to getter impurities, and an adhesive layer. 6. The method of claim 1 , further comprising providing, before the bonding, conductive structures on the working surface of the substrate. 7. The method of claim 1 , wherein the glass piece is adhesive bonded to the substrate through an adhesive material provided between the substrate and the glass piece before the bonding. 8. The method of claim 1 , wherein the glass piece is in-situ bonded to the substrate by pressing the glass piece and the substrate against each other, and wherein a temperature of the glass piece and a force exerted on the glass piece are controlled such that the fluidified glass material re-solidifies and the re-solidified glass material is bonded to the substrate. 9. The method of claim 1 , wherein the glass piece comprises a protrusion forming a grid matching with the grid formed by the cavity. 10. The method of claim 1 , further comprising thinning, after the bonding and before the separating, the substrate from a rear side which is opposite to the working surface. 11. The method of claim 10 , wherein the thinning stops at a buried edge of the glass piece. 12. The method of claim 10 , further comprising implanting, from the rear side, dopants to form at least one of a field stop structure, an emitter region for an IGBT, or a diode, and a highly doped drain region for a power MOSFET, after the thinning. 13. The method of claim 10 , further comprising thermally treating, after the thinning, the substrate at a temperature of at least 400 degrees Celsius. 14. The method of claim 10 , further comprising removing, before the thinning, excess portions of the glass layer outside the cavities to expose the working surface of the substrate. 15. The method of claim 14 , further comprising adhesive bonding a carrier to the substrate after providing conductive structures on the exposed working surface. 16. The method of claim 15 , further comprising annealing, after removing the carrier, the substrate at a temperature of at least 400 degrees Celsius. 17. The method of claim 1 , further comprising thinning, after the bonding and before the separating, the substrate from a rear side which is opposite to the working surface, wherein the thinning stops at an auxiliary layer lining the cavity. 18. The method of claim 1 , further comprising forming at least one of a power field effect transistor, diode, and IGBT in the semiconductor substrate. 19. A semiconductor device, comprising: an active semiconductor element formed in a single-crystalline semiconductor portion, the single-crystalline semiconductor portion having a working surface, a rear side surface opposite to the working surface and an edge surface connecting the working and rear side surfaces; and a glass piece comprising a portion extending from the working surface along and in direct contact with the edge surface of the single-crystalline semiconductor portion. 20. The semiconductor device of claim 19 , wherein the glass piece forms a continuous frame extending along the edge surface of the single-crystalline semiconductor portion. 21. The semiconductor device of claim 19 , further comprising an adhesive layer between the single-crystalline semiconductor portion and the glass piece, the adhesive layer adhesive bonding the glass piece with the single-crystalline semiconductor portion. 22. The semiconductor device of claim 19 , wherein the active semiconductor element is at least one of a power field effect transistor, an IGBT and a diode. 23. The semiconductor device of claim 19 , wherein the glass piece is free of hydrocarbon compounds.

Assignees

Inventors

Classifications

  • using bonding · CPC title

  • Manufacture or treatment · CPC title

  • formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

  • using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

  • H10W74/134Primary

    the encapsulations being in grooves in the semiconductor body · CPC title

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What does patent US9601376B2 cover?
A semiconductor device includes a glass piece and an active semiconductor element formed in a single-crystalline semiconductor portion. The single-crystalline semiconductor portion has a working surface, a rear side surface opposite to the working surface and an edge surface connecting the working and rear side surfaces. The glass piece has a portion extending along and in direct contact with t…
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H10W74/134. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 21 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).