UV-cure pre-treatment of carrier film for wafer dicing using hybrid laser scribing and plasma etch approach

Patent metadata

Field	Value
Publication number	US-9601375-B2
Application number	US-201514697391-A
Country	US
Kind code	B2
Filing date	Apr 27, 2015
Priority date	Apr 27, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits on a front side of the semiconductor wafer includes adhering a back side the semiconductor wafer on the dicing tape of a substrate carrier. Subsequent to adhering the semiconductor wafer on a dicing tape, the dicing tape is treated with a UV-cure process. Subsequent to treating the dicing tape with the UV-cure process, a dicing mask is formed on the front side of the semiconductor wafer, the dicing mask covering and protecting the integrated circuits. The dicing mask is patterned with a laser scribing process to provide gaps in the dicing mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the dicing mask layer to singulate the integrated circuits.

First claim

What is claimed is:

1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits on a front side of the semiconductor wafer, the method comprising:
adhering a back side the semiconductor wafer on the dicing tape of a substrate carrier;
subsequent to adhering the semiconductor wafer on a dicing tape, treating the dicing tape with a UV-cure process;
subsequent to treating the dicing tape with the UV-cure process, forming a dicing mask on the front side of the semiconductor wafer, the dicing mask covering and protecting the integrated circuits;
patterning the dicing mask with a laser scribing process to provide gaps in the dicing mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits; and
plasma etching the semiconductor wafer through the gaps in the dicing mask layer to singulate the integrated circuits.

2. The method of claim 1 , wherein treating the dicing tape with the UV-cure process comprises exposure to approximately 1-3 passes of a UV dose approximately in the range of 50 mJ to 300 mJ.

3. The method of claim 1 , wherein treating the dicing tape with the UV-cure process comprises permanently weakening an adhesion between the dicing tape of the substrate carrier and the back side of the semiconductor wafer.

4. The method of claim 1 , wherein forming the dicing mask comprises spin-coating a masking layer on the front side of the semiconductor wafer.

5. The method of claim 4 , further comprising:
subsequent to spin-coating the masking layer on the front side of the semiconductor wafer and prior to patterning the dicing mask with a laser scribing process, baking the masking layer.

6. The method of claim 4 , wherein spin-coating the masking layer comprises forming a water-soluble mask layer.

7. The method of claim 4 , wherein spin-coating the masking layer comprises forming a UV-curable mask layer.

8. The method of claim 1 , wherein forming the dicing mask comprises laminating a polymeric mask layer onto the front side of the semiconductor wafer by dry film vacuum lamination.

9. The method of claim 8 , wherein laminating the polymeric mask layer onto the front side of the semiconductor wafer by dry film vacuum lamination comprises heating the semiconductor wafer.

10. The method of claim 1 , further comprising:
subsequent to plasma etching the semiconductor wafer through the gaps in the dicing mask layer, performing a die pick of the singulated integrated circuits from the dicing tape of the substrate carrier.

11. The method of claim 10 , further comprising:
subsequent to plasma etching the semiconductor wafer through the gaps in the dicing mask layer and prior to performing the die pick, removing the dicing mask layer.

12. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits on a front side of the semiconductor wafer, the method comprising:
adhering a back side the semiconductor wafer on a dicing tape of a substrate carrier;
subsequent to adhering the semiconductor wafer on the dicing tape, forming a dicing mask on the front side of the semiconductor wafer, the dicing mask covering and protecting the integrated circuits;
subsequent to forming the dicing mask, treating the dicing tape with a UV-cure process;
subsequent to treating the dicing tape with the UV-cure process, patterning the dicing mask with a laser scribing process to provide gaps in the dicing mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits; and
plasma etching the semiconductor wafer through the gaps in the dicing mask layer to singulate the integrated circuits.

13. The method of claim 12 , wherein treating the dicing tape with the UV-cure process comprises exposure to approximately 1-3 passes of a UV dose approximately in the range of 50 mJ to 300 mJ.

14. The method of claim 12 , wherein treating the dicing tape with the UV-cure process comprises permanently weakening an adhesion between the dicing tape of the substrate carrier and the back side of the semiconductor wafer.

15. The method of claim 12 , wherein forming the dicing mask comprises laminating a polymeric mask layer onto the front side of the semiconductor wafer by dry film vacuum lamination.

16. The method of claim 12 , further comprising:
subsequent to plasma etching the semiconductor wafer through the gaps in the dicing mask layer, performing a die pick of the singulated integrated circuits from the dicing tape of the substrate carrier.

17. The method of claim 16 , further comprising:
subsequent to plasma etching the semiconductor wafer through the gaps in the dicing mask layer and prior to performing the die pick, removing the dicing mask layer.

Assignees

• Lei Wei-Sheng
• Eaton Brad
• Park Jungrae
• Kumar Ajay
• Papanu James S
• Kumar Prabhat
• Applied Materials Inc

Inventors

• Lei Wei-Sheng
• Eaton Brad
• Park Jungrae
• Kumar Ajay
• Papanu James S
• Kumar Prabhat

Classifications

• H10P72/7422

  used to protect an active side of a device or wafer · CPC title

• H10P72/7416

  used during dicing or grinding · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P72/7402 Primary

  Wafer tapes, e.g. grinding or dicing support tapes · CPC title

• H10P72/0468

  comprising a chamber adapted to a particular process · CPC title