Growing a III-V layer on silicon using aligned nano-scale patterns

Patent metadata

Field	Value
Publication number	US-9601328-B2
Application number	US-84254610-A
Country	US
Kind code	B2
Filing date	Jul 23, 2010
Priority date	Oct 8, 2009
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A method of forming an integrated circuit structure includes providing a wafer having a silicon substrate; forming a plurality of shallow trench isolation (STI) regions in the silicon substrate; and forming recesses by removing top portions of the silicon substrate between opposite sidewalls of the plurality of STI regions. Substantially all long sides of all recesses in the silicon substrate extend in a same direction. A III-V compound semiconductor material is then epitaxially grown in the recesses.

First claim

What is claimed is:

1. A method of forming an integrated circuit structure, the method comprising:
forming a plurality of shallow trench isolation (STI) regions in a silicon substrate;
forming recesses by removing top portions of the silicon substrate between opposite sidewalls of the plurality of STI regions, wherein substantially all long sides of all recesses in the silicon substrate extend in a same direction; and
performing an epitaxy using one of a first process condition and a second process condition based on a long-side direction of the recesses, wherein the first process condition is used to epitaxially grow a III-V compound semiconductor material in the recesses using a first set of process parameters if the long sides of the recesses are parallel to a <110> direction of the silicon substrate and the second process condition is used to epitaxially grow a III-V compound semiconductor material in the recesses using a second set of process parameters if the long sides of the recesses are parallel to a <1-10> direction of the silicon substrate, wherein the first and the second set of process parameters are chosen such that the III-V compound semiconductor material in the recesses has a higher defect density facing long sides of the respective recesses than facing short sides of the respective recesses.

2. The method of claim 1 , wherein the first process condition comprises a first growth temperature, and the second process condition comprises a second growth temperature lower than the first growth temperature.

3. The method of claim 1 , wherein the first process condition comprises a first V-to-III flow ratio, and the second process condition comprises a second V-to-III flow ratio higher than the first V-to-III flow ratio.

4. The method of claim 2 , wherein the first growth temperature is higher than 400° C., and the second growth temperature is lower than 400° C.

5. The method of claim 2 , wherein the first process condition further comprises a first V-to-III flow ratio, the second process condition further comprises a second V-to-III flow ratio higher than the first V-to-III flow ratio.

6. The method of claim 5 , wherein the first growth temperature is higher than 400° C., and the second growth temperature is lower than 400° C.

7. The method of claim 1 further comprising forming MOS devices at surfaces of the III-V compound semiconductor material in the recesses, wherein substantially all MOS devices extend in an additional direction perpendicular to the same direction.

8. The method of claim 1 , wherein the III-V compound semiconductor material is GaAs.

9. A method of forming an integrated circuit structure, the method comprising:
forming a first plurality of shallow trench isolation (STI) regions in a first silicon substrate, wherein the first silicon substrate has a (001) surface orientation;
forming first recesses extending into the first silicon substrate and between opposite sidewalls of the first plurality of STI regions, the first recesses having long sides and short sides shorter than the long sides, and the long sides extend in a <110> direction of the first silicon substrate; and
performing an epitaxy using a first process condition based on long-side directions of the first recesses, wherein the first process condition is used to epitaxially grow first III-V semiconductor films in the first recesses such that the first III-V semiconductor films in the first recesses have a higher defect density facing long sides of the respective first recesses than facing short sides of the respective first recesses.

10. The method of claim 9 further comprising:
forming a second plurality of STI regions in a second silicon substrate, wherein the second silicon substrate has a (001) surface orientation;
forming second recesses extending into the second silicon substrate and between opposite sidewalls of the second plurality of STI regions, the second recesses having long sides extend in a <1-10> direction of the second silicon substrate; and
performing an additional epitaxy using a second process condition based on long-side directions of the second recesses, wherein the second process condition is used to epitaxially grow second III-V semiconductor films in the second recesses such that the second III-V semiconductor films in the second recesses have a higher defect density facing long sides of the respective second recesses than facing short sides of the respective second recesses.

11. The method of claim 10 , wherein the first process condition comprises a first growth temperature, the second process condition comprises a second growth temperature lower than the first growth temperature.

12. The method of claim 10 , wherein the first process condition comprises a first V-to-III flow ratio, the second process condition comprises a second V-to-III flow ratio higher than the first V-to-III flow ratio.

13. The method of claim 11 , wherein the first growth temperature is higher than about 400° C., and the second growth temperature is lower than about 400° C.

14. The method of claim 13 , wherein the first growth temperature is between about 400° C. and about 600° C., and the second growth temperature is 200° C. and about 400° C.

15. A method of forming an integrated circuit structure, the method comprising:
forming a first plurality of shallow trench isolation (STI) regions in a first silicon substrate, wherein the first silicon substrate has a (001) surface orientation;
forming first recesses extending into the first silicon substrate and between opposite sidewalls of the first plurality of STI regions, the first recesses long sides extending in a <110> direction of the first silicon substrate;
forming a second plurality of STI regions in a second silicon substrate, wherein the second silicon substrate has a (001) surface orientation;
forming second recesses extending into the second silicon substrate and between opposite sidewalls of the second plurality of STI regions, the second recesses having long sides extending in a <110> direction of the second silicon substrate;
performing a first epitaxy using a first process condition to grow first GaAs films in the first recesses such that the first GaAs films in the first recesses have a higher defect density facing long sides of the respective first recesses than facing short sides of the respective first recesses; and
performing a second epitaxy using a second process condition to grow second GaAs films in the second recesses such that the second GaAs films in the second recesses have a higher defect density facing long sides of the respective second recesses than facing short sides of the respective second recesses, wherein the first process condition comprises a first temperature and a first As-to-Ga flow ratio, and the second process condition comprises a second temperature and a second As-to-Ga flow ratio, with the second temperature being lower than the first temperature, and the second As-to-Ga flow ratio being higher than the first As-to-Ga flow ratio.

16. The method of claim 15 , wherein the first epitaxy comprises a first nucleation stage during which pyramids of GaAs are formed, and the first process condition is used in the first nucleation stage, and a continued growth of the first GaAs films after the first nucleation stage is performed using a process condition different from the first process condition.

17. The method of claim 16 , wherein the second epitaxy comprises a second nucleation stage during which additional pyramids of GaAs are formed, and the second process condition is used in the second nuclea

Assignees

• Ko Chih-Hsin
• Wann Clement Hsingjen
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ko Chih-Hsin
• Wann Clement Hsingjen

Classifications

• H10P14/3466

  Crystal orientation · CPC title

• H10P14/2926

  Crystal orientations · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10P14/271

  characterised by the preparation of substrate for selective deposition · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title