Semiconductor memory device and memory system

Patent metadata

Field	Value
Publication number	US-9601210-B2
Application number	US-201615053939-A
Country	US
Kind code	B2
Filing date	Feb 25, 2016
Priority date	Feb 26, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A semiconductor memory device includes a first stack of memory cells above a substrate, the first stack including a first memory cell and a second memory cell above the first memory cell, a second stack of memory cells above the substrate, the second stack including a third memory cell, a word line connected to the first, second, and third memory cells, and a controller configured to output data stored in the first memory cell and data stored in the third memory cell during a first cycle, and output data stored in the second memory cell during a second cycle that is different from the first cycle.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a first stack of memory cells above a substrate, the first stack including a first memory cell and a second memory cell above the first memory cell;
a second stack of memory cells above the substrate, the second stack including a third memory cell;
a word line connected to the first, second, and third memory cells; and
a controller configured to output data stored in the first memory cell and data stored in the third memory cell during a first cycle, and output data stored in the second memory cell during a second cycle that is different from the first cycle.

2. The device according to claim 1 , wherein the second stack further includes a fourth memory cell stacked above the third memory cell, and the controller is configured to output data stored in the fourth memory cell during the second cycle.

3. The device according to claim 2 , wherein gate lengths of the first and third memory cells are substantially equal and smaller than gate lengths of the second and fourth memory cells, which are substantially equal.

4. The device according to claim 2 , wherein the data stored in the first, second, and third memory cells are output in connection with a single read operation, and the first cycle is after the second cycle.

5. The device according to claim 1 , wherein during the first cycle a first voltage is applied to the word line, and during the second cycle a second voltage higher than the first voltage is applied to the word line.

6. The device according to claim 1 , wherein the controller is configured to execute a programming operation that includes a program verify operation, on the first, second, and third memory cells, the program verify operation employing a first verify voltage for the first and third memory cells and a second verify voltage for the second memory cell.

7. The device according to claim 6 , wherein the controller repeats the programming operation with an increased programming voltage if the program verify operation fails, wherein the programming voltage is increased by a first step for the first and third memory cells and by a second step for the second memory cell, the second step being smaller than the first step.

8. The device according to claim 1 , wherein the controller is configured to execute a reading operation on the first, second, and third memory cells, and the reading operation includes the first and second cycles.

9. The device according to claim 1 , wherein the controller is configured to execute a reading operation on the first, second, and third memory cells and a re-reading operation on the first, second, and third memory cells, if the reading operation fails, the second cycle being part of the reading operation and the first cycle being part of the re-reading operation.

10. The device according to claim 9 , wherein during the re-reading operation, a voltage applied to the word line is lowered relative to that applied during the reading operation.

11. A method of executing a read operation in a semiconductor memory device having a first stack of memory cells above a substrate, the first stack including a first memory cell and a second memory cell above the first memory cell, a second stack of memory cells above the substrate, the second stack including a third memory cell, and a word line connected to the first, second, and third memory cells, said method comprising:
reading first data stored in the first memory cell and third data stored in the third memory cell and outputting the first data and the third data during a first cycle; and
reading second data stored in the second memory cell and outputting the second data during a second cycle that is different from the first cycle.

12. The method according to claim 11 , wherein the second stack further includes a fourth memory cell stacked above the third memory cell, and data stored in the fourth memory cell is read and output during the second cycle along with the second data.

13. The method according to claim 12 , wherein gate lengths of the first and third memory cells are substantially equal and smaller than gate lengths of the second and fourth memory cells, which are substantially equal.

14. The method according to claim 11 , wherein the first data and the second data are read and output in connection with a single read operation, and the first cycle is after the second cycle.

15. The method according to claim 11 , wherein during the reading of the first data, a first voltage is applied to the word line, and during reading of the second data, a second voltage higher than the first voltage is applied to the word line.

Assignees

• Toshiba Kk

Inventors

• Ochi Yusuke
• Shirakawa Masanobu

Classifications

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title