Semiconductor memory device and operating method thereof

Patent metadata

Field	Value
Publication number	US-2016019969-A1
Application number	US-201414572717-A
Country	US
Kind code	A1
Filing date	Dec 16, 2014
Priority date	Jul 15, 2014
Publication date	Jan 21, 2016
Grant date	—

Abstract

A semiconductor memory device according to an embodiment of the present invention includes a first cell string and a second cell string coupled to a first word line group and a second word line group, respectively. An operating method of the semiconductor memory device may include forming a channel in the second cell string by applying a pass voltage to the second word line group, reflecting data of a selected memory cell coupled to a selected word line of the first word line group, among memory cells of the first cell string, on the channel of the second cell string through the bit line, and determining the data of the selected memory cell by sensing a quantity of electric charge of the second cell string through the bit line.

First claim

What is claimed is:

1 . An operating method of a semiconductor memory device including a first cell string and a second cell string sharing a bit line and coupled to a first word line group and a second word line group, respectively, the operating method comprising:
forming a channel in the second cell string by applying a first pass voltage to the second word line group; reflecting data of a selected memory cell coupled to a selected word line of the first word line group, among memory cells of the first cell string, on the channel of the second cell string through the bit line; and determining the data of the selected memory cell by sensing a quantity of electric charge of the second cell string through the bit line.

2 . The operating method of claim 1 , wherein the forming of the channel in the second cell string comprises:
applying a bit line voltage to the bit line; and initializing the channel of the second cell string in response to the bit line voltage by electrically connecting the second cell string to the bit line.

3 . The operating method of claim 2 , wherein the reflecting of the data of the selected memory cell on the channel of the second cell string comprises:
reflecting the data of the selected memory cell on the bit line, wherein the quantity of electric charge of the second cell string varies with a voltage of the bit line.

4 . The operating method of claim 1 , further comprising:
electrically separating the second cell string from the bit line after the data of the selected memory cell is reflected on the channel of the second cell string.

5 . The operating method of claim 1 , wherein the determining of the data of the selected memory cell comprises:
forming the channel in the second cell string by applying a second pass voltage to the second word line group; and electrically connecting the channel of the second cell string to the bit line to reflect the quantity of electric charge of the second cell string on the bit line.

6 . The operating method of claim 5 , wherein the determining of the data of the selected memory cell further comprises:
determining the data of the selected memory cell by sensing a voltage of the bit line.

7 . The operating method of claim 1 , wherein, in the determining of the data of the selected memory cell, the first cell string is electrically separated from the bit line.

8 . The operating method of claim 1 , further comprising:
forming a channel in the first cell string by applying a bit line voltage to the bit line and applying a second pass voltage to the first word line group; and initializing the channel of the first cell string in response to the bit line voltage by electrically connecting the first cell string to the bit line.

9 . The operating method of claim 1 , wherein the determining of the data of the selected memory cell is performed within a predetermined period of time after the reflecting of the data of the selected memory cell on the channel of the second cell string.

10 . A semiconductor memory device, comprising:
a first cell string coupled to a first word line group; a second cell string coupled to a second word line group and suitable for sharing a bit line with the first cell string; and a peripheral circuit suitable for forming a channel in the second cell string by applying a pass voltage to the second word line group, reflecting data of a selected memory cell in the first cell string on the channel of the second cell string through the bit line, and determining the data of the selected memory cell by sensing a quantity of electric charge of the channel of the second cell string through the bit line.

11 . The semiconductor memory device of claim 10 , wherein the peripheral circuit comprises:
an address decoder coupled to the first and second word line groups; and a page buffer suitable for providing a bit line voltage to the bit line, wherein the address decoder is suitable for applying the pass voltage to the second word line group to form the channel in the second cell string, and electrically connecting the second cell string to the bit line to initialize the channel of the second cell string in response to the bit line voltage.

12 . The semiconductor memory device of claim 11 , wherein the address decoder selects a word line from the first word line group, electrically connects the first cell string to the bit line and reflects the data of the selected memory cell on the bit line, and
the quantity of electric charge of the channel of the second cell string varies with a voltage of the bit line.

13 . An operating method of a semiconductor memory device, comprising:
reflecting data bits of a first page in first cell strings on channels of second cell strings through bit lines, wherein the first and second cell strings are suitable for sharing bit lines and coupled to a first word line group and a second word line group, respectively; determining and storing the data bits of the first page by sensing a quantity of electric charge of the channels of the second cell strings through the bit lines; and outputting the data bits of the first page.

14 . The operating method of claim 13 , further comprising:
reflecting data bits of a second page in the first cell strings on channels of third cell strings through the bit lines during the outputting of the data bits of the first page, wherein the third cell strings are coupled to a third word line group and suitable for sharing the bit lines with the first cell strings.

15 . The operating method of claim 14 , further comprising:
determining and storing the data bits of the second page by sensing a quantity of electric charge of the channels of the third cell strings through the bit lines; and outputting the data bits of the second page.

16 . The operating method of claim 15 , wherein the sensing of the quantity of electric charge of the channels of the third cell strings is performed during the outputting of the data bits of the first page.

17 . The operating method of claim 13 , further comprising:
reflecting data bits of a second page of the first cell strings on the channels of the second cell strings through the bit lines during the outputting of the data bits of the first page.

18 . The operating method of claim 17 , further comprising:
determining and storing the data bits of the second page by sensing the quantity of electric charge of the channels of the second cell strings through the bit lines; and outputting the data bits of the second page.

19 . The operating method of claim 13 , further comprising:
reflecting data bits of a second page of third cell strings on the channels of the second cell strings through the bit lines during the outputting of the data bits of the first page; determining and storing the data bits of the second page by sensing the quantity of electric charge of the channels of the second cell strings through the bit lines; and outputting the data bits of the second page, wherein the third cell strings are coupled to a third word line group and suitable for sharing the bit lines with the second cell strings.

20 . The operating method of claim 13 , further comprising:
reflecting data bits of a second page of third cell strings on channels of fourth cell strings through the bit lines during the outputting of the data bits of the first page; determining and storing the data bits of the second page by sensing a quantity of electric charge of the channels of the fourth cell strings thr

Assignees

• Sk Hynix Inc

Inventors

• Lim In Geun
• Lee Min Kyu

Classifications

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/20 Primary

  Initialising; Data preset; Chip identification · CPC title