Technique for performing arbitrary width integer arithmetic operations using fixed width elements

Patent metadata

Field	Value
Publication number	US-9600235-B2
Application number	US-201314026829-A
Country	US
Kind code	B2
Filing date	Sep 13, 2013
Priority date	Sep 13, 2013
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

One embodiment of the present invention includes a method for performing arithmetic operations on arbitrary width integers using fixed width elements. The method includes receiving a plurality of input operands, segmenting each input operand into multiple sectors, performing a plurality of multiply-add operations based on the multiple sectors to generate a plurality of multiply-add operation results, and combining the multiply-add operation results to generate a final result. One advantage of the disclosed embodiments is that, by using a common fused floating point multiply-add unit to perform arithmetic operations on integers of arbitrary width, the method avoids the area and power penalty of having additional dedicated integer units.

First claim

The invention claimed is:

1. A computer-implemented method for performing integer arithmetic operations, the method comprising:
receiving a plurality of input operands;
segmenting, via a processor, each input operand into multiple sectors;
performing a plurality of multiply-add operations based on the multiple sectors to generate a plurality of multiply-add operation results; and
combining the multiply-add operation results to generate a final result.

2. The computer-implemented method of claim 1 further comprising analyzing the size of each input operand included in the plurality of input operands to determine how many multiply-add operations should be included in the plurality of multiply-add operations.

3. The computer-implemented method of claim 1 , wherein performing the plurality of multiply-add operations comprises performing a multiply component of a first multiply-add operation by multiplying a first sector of a first input operand included in the plurality of input operands with a first sector of a second input operand included in the plurality of input operands to generate a first product.

4. The computer-implemented method of claim 3 , wherein performing the plurality of multiply-add operations comprises performing an add component of the first multiply-add operation by:
setting a relative exponent difference between the first sector of a third input operand included in the plurality of input operands and the first product to zero in order to align the first sector of the third input operand with the first product; and
adding the first sector of the third input operand to the first product to generate a first partial result.

5. The computer-implemented method of claim 4 , wherein performing the plurality of multiply-add operations comprises performing a multiply component of a second multiply-add operation by multiplying a second sector of the first input operand with the first sector of the second input operand to generate a second product.

6. The computer-implemented method of claim 5 , wherein performing the plurality of multiply-add operations comprises performing an add component of the second multiply-add operation by:
selecting a portion of the first partial result as an addend for the second multiply- add operation;
setting a relative exponent difference between the addend and the second product to zero in order to align the addend with the second product; and
adding the addend to the second product to generate a second partial result.

7. The computer-implemented method of claim 6 , wherein performing the plurality of multiply-add operations comprises performing a multiply component of a final multiply-add operation by multiplying a final sector of the first input operand with a final sector of the second operand to generate a final product.

8. The computer-implemented method of claim 7 , wherein performing the plurality of multiply-add operations comprises performing an add component of the final multiply-add operation by:
selecting a portion of a prior result as an addend for the final multiply-add operation;
setting a relative exponent difference between the addend and the final product to zero in order to align the addend with the final product; and
adding the addend to the final product to generate a final partial result.

9. The computer-implemented method of claim 8 , wherein combining the multiply-add operation results to generate a final result comprises combining the first partial result, the second partial result, the prior partial result, and the final partial result to generate the final result.

10. A system for performing integer arithmetic operations, the system comprising:
a plurality of formatting elements, wherein each formatting element is configured to receive one or more input operands;
an operand processing element configured to segment each input operand into sectors;
a multiplier array configured to perform a plurality of multiply operations with the sectors of the input operands to generate a plurality of multiply results;
an adder element configured to perform summing operations based on the plurality of multiply results and one or more addends to generate a plurality of partial results; and
a multiplex element configured to cause the plurality of partial results to be combined to generate a final result.

11. The system of claim 10 , wherein the operand processing element is further configured to analyze the size of each input operand to determine the number of multiply-add operations in the plurality of multiply-add operations.

12. The system of claim 10 , wherein the multiplier array is further configured to multiply a first sector of a first input operand with a first sector of a second input operand to generate a first product.

13. The system of claim 12 , further comprising:
an exponent path element and a shifter that are configured to set a relative exponent difference between the first sector of a third input operand and the first product to zero in order to align the first sector of the third input operand with the first product,
wherein the adder element is further configured to add the first sector of the third input operand to the first product to generate a first partial result.

14. The system of claim 13 , wherein the multiplier array is further configured to multiply a second sector of the first input operand with the first sector of the second input operand to generate a second product.

15. The system of claim 14 , further comprising:
a second multiplex element configured to selecting a portion of the first partial result as an addend,
wherein the exponent path element and the shifter are further configured to set a relative exponent difference between the addend and the second product to zero in order to align the addend with the second product, and
wherein the adder element is further configured to add the addend to the second product to generate a second partial result.

16. The system of claim 15 , wherein the multiplier array is further configured to multiply a final sector of the first input operand with a final sector of the second operand to generate a final product.

17. The system of claim 16 , wherein:
the second multiplex element is further configured to select a portion of a prior result as an addend,
the exponent path element and the shifter are further configured to set a relative exponent difference between the addend and the final product to zero in order to align the addend with the final product, and
the adder element is further configured to add the addend to the final product to generate a final partial result.

18. The system of claim 10 , wherein the multiplex element is further configured to cause the partial result, the second partial result, the prior partial result, and the final partial result to be combined to generate the final result.

19. A computing device, including:
a memory;
a processing unit coupled to the memory and including a subsystem configured to perform integer arithmetic operations, the subsystem having:
a plurality of formatting elements, wherein each formatting element is configured to receive one or more input operands;
an operand processing element configured to segment each input operand into sectors; and
one or more elements configured to perform a plurality of multiply-add operations on the sectors to generate a plurality of results.

20. The computing device of claim 19 , wherein the processing element comprises a central processing unit, a parallel processing unit, or

Assignees

• Nvidia Corp

Inventors

• Iyer Srinivasan
• Fetterman Michael Alan
• Tannenbaum David Conrad

Classifications

• G06F7/525 Primary

  in serial-serial fashion, i.e. both operands being entered serially (G06F7/533 takes precedence) · CPC title

• G06F2207/3824

  Accepting both fixed-point and floating-point numbers · CPC title