Capacitive discharge circuit for touch sensitive screen

Patent metadata

Field	Value
Publication number	US-2016124541-A1
Application number	US-201414531631-A
Country	US
Kind code	A1
Filing date	Nov 3, 2014
Priority date	Nov 3, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

A capacitive discharge circuit includes a line having a capacitance, a switched capacitor circuit including a capacitor, a switched circuit coupled to the line, and a voltage regulator coupled between the switched capacitor circuit and the switched circuit. A controller operates the switched capacitor circuit and switched circuit to in a first phase, charge the capacitor by coupling the capacitor between a common mode and a power supply, and in a second phase, discharge the capacitor by coupling the voltage regulator in series with the capacitor between the power supply node a ground. The controller is also configured to in a third phase, charge the capacitor by coupling the capacitor between the common mode and the power supply, and in a fourth phase, share charge between the line and the capacitor by coupling the voltage regulator and the capacitor in series between the line and the ground.

First claim

1 . A capacitive discharge circuit comprising:
a line having a capacitance associated therewith; a switched capacitor circuit comprising a capacitor; a switched circuit coupled to the line; a voltage regulator circuit coupled between the switched capacitor circuit and the switched circuit; and a controller configured to operate the switched capacitor circuit and the switched circuit so as to:
in a first phase, charge the capacitor by coupling the capacitor between a common mode node and a power supply node,
in a second phase, discharge the capacitor by coupling the voltage regulator circuit in series with the capacitor between the power supply node and a ground node,
in a third phase, charge the capacitor by coupling the capacitor between the common mode node and the power supply node, and
in a fourth phase, share charge between the line and the capacitor by coupling the voltage regulator circuit and the capacitor in series between the line and the ground node.

2 . The capacitive discharge circuit of claim 1 , wherein the controller, before performing the third and fourth phases, is configured to repeat the first and second phases if an output of the voltage regulator circuit is less than a regulator threshold voltage.

3 . The capacitive discharge circuit of claim 1 , wherein the controller is configured to repeat the first and second phases a plurality of times before proceeding to the third phase.

4 . The capacitive discharge circuit of claim 1 , wherein the controller is configured to repeat the third and fourth phases until a voltage on the line is less than a line threshold voltage.

5 . The capacitive discharge circuit of claim 1 , wherein the controller is configured to repeat the third and fourth phases at least twice.

6 . The capacitive discharge circuit of claim 1 , wherein the voltage regulator circuit includes an input coupled to the common mode node and is configured to output a regulator voltage that is at most equal to a regulator threshold voltage.

7 . The capacitive discharge circuit of claim 1 , wherein the voltage regulator circuit comprises:
an operational amplifier having a first input coupled to the common mode node, a second input coupled to the switched capacitor circuit, and an output;
a transistor having a first conduction terminal coupled to the switched circuit, a second conduction terminal coupled to the switched capacitor circuit, and a control terminal coupled to the output of the operational amplifier.

8 . The capacitive discharge circuit of claim 1 , wherein the switched circuit comprises a switch circuit having inputs coupled to the line and to the power supply node, and an output coupled to the voltage regulator circuit.

9 . The capacitive discharge circuit of claim 1 , wherein the switched capacitor circuit comprises:
a first switch circuit having inputs coupled to the voltage regulator circuit and to the common mode node, and an output coupled to a first terminal of the capacitor; and a second switch circuit having inputs coupled to the power supply node and to the ground node, and an output coupled to a second terminal of the capacitor.

10 . An electronic device comprising:
a touch sensitive display; an input line coupled to the touch sensitive display; a voltage regulator circuit; a capacitor having first and second terminals; a first switch circuit having inputs coupled to the voltage regulator circuit and to a common mode node, and an output coupled to the first terminal of the capacitor; a second switch circuit having inputs coupled to a power supply node and to a ground node, and an output coupled to the second terminal of the capacitor; and a third switch circuit having inputs coupled to the input line and to the power supply node, and an output coupled to the voltage regulator circuit.

11 . The electronic device of claim 10 , wherein the first switch circuit comprises a single pole double throw switch having inputs coupled to the voltage regulator circuit and to the common mode node, and an output coupled to the first terminal of the capacitor.

12 . The electronic device of claim 10 , wherein the first switch circuit comprises a first switch coupled between the voltage regulator circuit and the first terminal of the capacitor, and a second switch coupled between the common mode node and the first terminal of the capacitor.

13 . The electronic device of claim 10 , wherein the second switch circuit comprises a single pole double throw switch having inputs coupled to the power supply node and to the ground node, and an output coupled to the second terminal of the capacitor.

14 . The electronic device of claim 10 , wherein the second switch circuit comprises a first switch coupled between the power supply node and the second terminal of the capacitor, and a second switch coupled between the ground node and the second terminal of the capacitor.

15 . The electronic device of claim 10 , wherein the third switch circuit comprises a single pole double throw switch having inputs coupled to the input line and to the power supply node, and an output coupled to the voltage regulator circuit.

16 . The electronic device of claim 10 , wherein the third switch circuit comprises a first switch coupled between the input line and the voltage regulator circuit, and a second switch coupled between the power supply node and the voltage regulator circuit.

17 . The electronic device of claim 10 , wherein the voltage regulator circuit comprises:
an operational amplifier having a first input coupled to the common mode node, a second input coupled to the first switch circuit, and an output; a field effect transistor having a source terminal coupled to the third switch circuit, a drain terminal coupled to first switch circuit, and a gate terminal coupled to the output of the operational amplifier.

18 . A method of discharging a capacitance on a line comprising:
in a first phase, charge a capacitor by coupling the capacitor between a common mode node and a power supply node, in a second phase, discharge the capacitor by coupling a voltage regulator circuit in series with the capacitor between the power supply node and a ground node, in a third phase, charge the capacitor by coupling the capacitor between the common mode node and the power supply node, and in a fourth phase, share charge between the line and the capacitor by coupling the voltage regulator circuit and capacitor in series between the line and the ground node.

19 . The method of claim 18 , further comprising before performing the third and fourth phases, repeating the first and second phases if an output of the voltage regulator is less than a regulator threshold voltage.

20 . The method of claim 18 , further comprising repeating the first and second phases a plurality of times before proceed to the third phase.

21 . The method of claim 18 , further comprising repeating the third and fourth phases until a voltage on the line is less than a line threshold voltage.

22 . The method of claim 18 , further comprising repeating the third and fourth phases at least twice.

Assignees

• St Microelectronics Asia

Inventors

• Cheong Chee Weng
• Guo Dianbo
• Tan Kien Beng
• Guedon Yannick

Classifications

• G06F3/041

  Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means · CPC title

• G06F3/0418

  for error correction or compensation, e.g. based on parallax, calibration or alignment · CPC title

• G09G5/18

  Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12}) · CPC title

• G06F3/044 Primary

  by capacitive means · CPC title

• G06F3/0446 Primary

  using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes · CPC title