Architecture, system, method, and computer-accessible medium for partial-scan testing

Patent metadata

Field	Value
Publication number	US-9599671-B2
Application number	US-201213368926-A
Country	US
Kind code	B2
Filing date	Feb 8, 2012
Priority date	Feb 24, 2011
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

Exemplary method, computer-accessible medium, test architecture, and system can be provided for a partial-scan test of at least one integrated circuit. For example, it is possible to obtain a plurality of test cubes using a first combinational automatic test pattern generation (ATPG) and identify at least one flip-flop of the integrated circuit using the test cubes to convert to a non-scan flip-flop and facilitate the partial-scan test to utilize the cubes without a utilization of a sequential ATPG or a second combinational ATPG.

First claim

What is claimed is:

1. A method for performing a partial-scan test of at least one integrated circuit, comprising:
obtaining a plurality of test cubes including at least one justification cube of the at least one integrated circuit;
identifying a plurality of scan flip-flops in the test cubes; and
with a cube merging procedure, (i) identifying each previously-identified scan flip-flop of the integrated circuit that is individually convertible to a non-scan flip-flop, and (ii) performing the partial-scan test based on only the test cubes;
wherein the identification procedure of each previously-identified scan flip-flop further includes identifying a particular previously-identified scan flip-flop (i) where there are no 0-1 conflicts between a particular test cube that requires the particular previously-identified scan flip-flop to be at a particular value and a particular justification cube associated with the particular previously-identified scan flip-flop for the particular value, and (ii) where the particular justification cube does not specify a bit of the particular previously-identified scan flip-flop to a 0 or a 1.

2. The method of claim 1 , further comprising post-processing of the test cubes so as perform the partial-scan test based on only the test cubes.

3. The method of claim 1 , wherein the partial-scan test includes a performance of a controllability and an observability associated with a full-scan test of the at least one integrated circuit.

4. The method of claim 1 , wherein the at least one justification cube includes a plurality of justification cubes, and wherein the identification of each previously-identified scan flip-flop uses the justification cubes to justify each previously-identified scan flip-flop to a value and includes merging the justification cubes.

5. The method of claim 1 , wherein the identification of each previously-identified scan flip-flop further includes identifying at least one pair of previously-identified scan flip-flops that is convertible to non-scanned flip-flops.

6. The method of claim 5 , wherein identifying the at least one pair of previously-identified scan flip-flops includes merging the test cubes associated with the at least one pair of previously-identified scan flip-flops.

7. The method of claim 5 , wherein the second identification of each previously-identified scan flip-flop further includes identifying at least one group of previously-identified scan flip-flops that is convertible to non-scanned flip-flops.

8. The method of claim 7 , wherein identifying the at least one group of previously-identified scan flip-flops includes mapping the previously-identified scan flip-flops of the at least one group of previously-identified scan flip-flops onto a maximum independent set problem.

9. The method of claim 8 , wherein mapping the previously-identified scan flip-flops onto the maximum independent set problem includes using a conflict graph.

10. The method of claim 5 , wherein the identification of each previously-identified scan flip-flop further includes identifying the at least one pair of previously-identified scan flip-flops where (i) a previously-identified scan first flip-flop of the at least one pair of the previously-identified scan flip-flops and a second previously-identified scan flip-flop of the at least one pair of the previously-identified scan flip-flops are individually convertible into non-scanned flip-flops, (ii) a first justification cube associated with the first previously-identified scan flip-flop and a second justification cube associated with the second previously-identified scan flip-flop are non-conflicting when two bits corresponding to the first previously-identified scan flip-flop and the second previously-identified scan flip-flop are specified by a particular test cube, and (iii) a justification cube for one of the first previously-identified scan flip-flop or the second previously-identified scan flip-flop does not specify the other of the first previously-identified scan flip-flop or the second previously-identified scan flip-flop.

11. A non-transitory computer readable medium for performing a partial-scan test of at least one integrated circuit including instructions thereon that are accessible by a hardware processing arrangement, wherein, when the processing arrangement executes the instructions, the processing arrangement is configured to:
obtain a plurality of test cubes including at least one justification cube of the at least one integrated circuit;
identify a plurality of scan flip-flops in the test cubes; and
with a cube merging procedure, (i) identify each previously-identified scan flip-flop of the integrated circuit that is individually convertible to a non-scan flip-flop, and (ii) perform the partial-scan test based on only the test cubes;
wherein the identification procedure of each previously-identified scan flip-flop further includes identifying a particular previously-identified scan flip-flop (i) where there are no 0-1 conflicts between a particular test cube that requires the particular previously-identified scan flip-flop to be at a particular value and a particular justification cube associated with the particular previously-identified scan flip-flop for the particular value, and (ii) where the particular justification cube does not specify a bit of the particular previously-identified scan flip-flop to a 0 or a 1.

12. The non-transitory computer readable medium of claim 11 , wherein the non-transitory computer readable medium is further configured to perform a post-processing of the plurality of test cubes so as perform the partial-scan test based on only the test cubes.

13. The non-transitory computer readable medium of claim 11 , wherein the partial-scan test includes a performance of a controllability and an observability associated with a full-scan test of the at least on integrated circuit.

14. The non-transitory computer readable medium of claim 11 , the at least one justification cube includes a plurality of justification cubes, and wherein identifying each previously-identified scan flip-flop uses the justification cubes to justify each previously-identified scan flip-flop to a value and includes merging the plurality of justification cubes.

15. The non-transitory computer readable medium of claim 11 , wherein the identification of each previously-identified scan flip-flop further includes identifying at least one pair of previously-identified scan flip-flops that is convertible to non-scanned flip-flops.

16. The non-transitory computer readable medium of claim 15 , wherein identifying the at least one pair of previously-identified scan flip-flops includes merging the test cubes associated with the at least one pair of previously-identified scan flip-flops.

17. The non-transitory computer readable medium of claim 15 , wherein the identification of each previously-identified scan flip-flop further includes identifying at least one group of previously-identified scan flip-flops that is convertible to non-scanned flip-flops.

18. The non-transitory computer readable medium of claim 17 , wherein identifying the at least one group of previously-identified scan flip-flops includes mapping the previously-identified scan flip-flops of the at least one group of previously-identified scan flip-flops onto a maximum independent set problem.

19. The non-transitory computer readable medium of claim 18 , wherein mapping the previously-identified scan flip-flops onto the maximum independent set problem includes using a conflict graph.

Assignees

• Sinanoglu Ozgur
• Univ New York

Inventors

• Sinanoglu Ozgur

Classifications

• G01R31/318544 Primary

  Scanning methods, algorithms and patterns (G01R31/3183 takes precedence) · CPC title

• G01R31/318547

  Data generators or compressors · CPC title

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/318586

  with partial scan or non-scannable parts · CPC title