Circuit board having a signal layer with signal traces and a reference plane with an additional signal trace larger than the signal traces

Patent metadata

Field	Value
Publication number	US-9596749-B2
Application number	US-201414567916-A
Country	US
Kind code	B2
Filing date	Dec 11, 2014
Priority date	Dec 11, 2014
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

Techniques for routing signal traces in a circuit board are described. An example of an electronic device in accordance with the described techniques includes a circuit board comprising a plurality of conductive layers. The conductive layers include a signal layer and a reference plane. The signal layer includes signal traces and the reference plane includes an additional signal trace.

First claim

What is claimed is:

1. An electronic device, comprising:
a circuit board comprising a plurality of conductive layers, the plurality of conductive layers comprising:
a signal layer comprising signal traces; and
a reference plane comprising an additional signal trace, wherein the additional signal trace is larger than the signal traces in the signal layer;
wherein the additional signal trace is one of a pair of additional signal traces used for differential signaling and wherein the pair of additional signal traces have a same impedance as the signal traces in the signal layer.

2. The electronic device of claim 1 , wherein a length of the additional signal trace is greater than approximately 7 inches and the additional signal trace is arranged to transmit a differential signal with a data rate greater than approximately 5 Gigabits per second (Gbps).

3. The electronic device of claim 1 , wherein the additional signal trace is to transmit a 10 Gbps Universal Serial Bus (USB) signal.

4. The electronic device of claim 1 , wherein a thickness of the additional signal trace is approximately 2 to 4 times the thickness of the respective signal traces in the signal layer.

5. The electronic device of claim 1 , wherein a width of the additional signal trace is approximately 2 to 4 times the width of the respective signal traces in the signal layer.

6. The electronic device of claim 1 , wherein a thickness of the respective signal traces in the signal layer is approximately 0.4 to 0.6 mils and a thickness of the additional signal trace is approximately 1.2 to 1.6 mils.

7. The electronic device of claim 1 , wherein a width of the respective signal traces in the signal layer is approximately 2 to 5 mils and a width of the additional signal trace is approximately 8 to 10 mils.

8. The electronic device of claim 1 , wherein the additional signal trace is angled relative to the respective signal traces in the signal layer.

9. A multiple-layer circuit board, comprising:
a first conductive layer comprising signal traces; and
a second conductive layer separated from the first conductive layer by a dielectric layer, the second conductive layer comprising a reference plane and an additional signal trace, wherein the second conductive layer is thicker than the first conductive layer;
wherein the additional signal trace is one of a pair of additional signal traces used for differential signaling and wherein the pair of additional signal traces have a same impedance as the signal traces in the first conductive layer.

10. The multiple-layer circuit board of claim 9 , wherein the additional signal trace is angled relative to the respective signal traces in the first conductive layer.

11. The multiple-layer circuit board of claim 9 , wherein a length of the additional signal trace is greater than approximately 7 inches and the additional signal trace is to transmit a differential signal with a data rate greater than 5 Gigabits per second.

12. The multiple-layer circuit board of claim 9 , wherein the additional signal trace is to transmit a Universal Serial Bus (USB) signal.

13. The multiple-layer circuit board of claim 9 , wherein a thickness of the second conductive layer is approximately 2 to 4 times the thickness of the first conductive layer and a width of the additional signal trace is approximately 2 to 4 times the width of the respective signal traces in the first conductive layer.

14. The multiple-layer circuit board of claim 9 , wherein a thickness of the respective signal traces in the first conductive layer is approximately 0.4 to 0.6 mils and a thickness of the additional signal trace is approximately 1.2 to 1.6 mils.

15. The multiple-layer circuit board of claim 9 , wherein a width of the respective signal traces in the first conductive layer is approximately 2 to 5 mils and a width of the additional signal trace is approximately 8 to 10 mils.

16. A method of manufacturing a printed circuit board (PCB), comprising:
forming a first conductive layer comprising signal traces;
forming a dielectric layer; and
forming a second conductive layer comprising a reference plane and an additional signal trace that is larger than the respective signal traces in the first conductive layer;
wherein the additional signal trace is one of a pair of additional signal traces used for differential signaling and wherein the pair of additional signal traces have approximately a same impedance as the signal traces in the first conductive layer.

17. The method of claim 16 , wherein a length of the additional signal trace is greater than approximately 7 inches and the additional signal trace is to transmit a differential signal with a data rate greater than 5 Gigabits per second.

18. The method of claim 16 , wherein forming the additional signal trace comprises forming the additional signal trace at an angle relative to the signal traces in the first conductive layer.

19. The method of claim 16 , wherein a width of the respective signal traces in the first conductive layer is approximately 2 to 5 mils and a width of the additional signal traces is approximately 8 to 10 mils.

20. The method of claim 16 , wherein a thickness of the signal traces in the first conductive layer is approximately 0.4 to 0.6 mils and a thickness of the additional signal trace is approximately 1.2 to 1.6 mils.

21. The method of claim 16 , wherein a thickness of the second conductive layer is approximately 2 to 4 times the thickness of the first conductive layer and a width of the additional signal trace is approximately 2 to 4 times the width of the respective signal traces in the first conductive layer.

Assignees

• Intel Corp

Inventors

• Chen Kuan-Yu
• Ling Yun
• Abdullah Mohd Muhaiyiddin Bin
• Kong Jackson Chung Peng
• Chen Chung-Hao
• Hsu Hao-Han
• Li Xiang

Classifications

• H01P11/003

  Manufacturing lines with conductors on a substrate, e.g. strip lines, slot lines · CPC title

• H05K1/0216

  Reduction of cross-talk, noise or electromagnetic interference (grounding H05K1/0215) · CPC title

• H05K1/0242 Primary

  Structural details of individual signal conductors, e.g. related to the skin effect · CPC title

• H05K3/4644

  by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title

• H05K1/0245

  Lay-out of balanced signal pairs, e.g. differential lines or twisted lines · CPC title