Cross point switch

Patent metadata

Field	Value
Publication number	US-9595968-B2
Application number	US-201514882262-A
Country	US
Kind code	B2
Filing date	Oct 13, 2015
Priority date	Jun 30, 2006
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

A cross point switch, in accordance with one embodiment, includes a plurality of tri-state repeaters coupled to form a plurality of multiplexers. Each set of corresponding tri-state repeaters in the plurality of multiplexers share a front end module such that delay through the cross point switch due to input capacitance is reduced as compared to conventional cross point switches.

First claim

What is claimed is:

1. A circuit, comprising:
an input node operable to receive an input signal;
an output node;
an enable circuit operable to receive an enable signal;
a first drive circuit coupled to the input node, the enable circuit, and the output node; and
a second drive circuit coupled to the input node, the enable circuit, and the output node, wherein if the enable signal is in a first state, one of the first drive circuit or the second drive circuit is operable for a period of time to drive at the output node a signal that represents the input signal, wherein the period of time terminates independently of the input signal, and wherein if the enable signal is in a second state, the output node is operable in an impedance state.

2. The circuit of claim 1 , further comprising:
a keeper circuit coupled to the enable circuit and further coupled between the input node and the output node.

3. The circuit of claim 1 , wherein the first drive circuit comprises:
a NAND gate coupled to the enable circuit and including a first output node;
an output drive transistor coupled to the first output node of the NAND gate;
a rising edge delay circuit coupled to the first output node of the NAND gate and the enable circuit; and
a delay circuit coupled in parallel with a portion of the rising edge delay circuit.

4. The circuit of claim 3 , wherein the first drive circuit further comprises:
a latch circuit coupled to the enable circuit, the NAND gate, and the rising edge delay circuit; and
a falling edge reset circuit coupled to the enable circuit and the second drive circuit.

5. The circuit of claim 1 , wherein the second drive circuit comprises:
a NOR gate coupled to the enable circuit and including a first output node;
an output drive transistor coupled to the first output node of the NOR gate;
a falling edge delay circuit coupled to the first output node of the NOR gate and the enable circuit; and
a delay circuit coupled in parallel with a portion of the falling edge delay circuit.

6. The circuit of claim 5 , wherein the second drive circuit further comprises:
a latch circuit coupled to the enable circuit, the NOR gate, and the falling edge delay circuit; and
a rising edge reset circuit coupled to the enable circuit and the first drive circuit.

7. A circuit, comprising:
an input node operable to receive an input signal;
an output node;
an enable circuit operable to receive an enable signal;
a first means for driving coupled to the input node, the enable circuit, and the output node; and
a second means for driving coupled to the input node, the enable circuit, and the output node, wherein if the enable signal is in a first state, one of the first means for driving or the second means for driving is operable for a period of time to drive at the output node a signal that represents the input signal, wherein the period of time terminates independently of the input signal, and wherein if the enable signal is in a second state, the output node is operable in an impedance state.

8. The circuit of claim 7 , further comprising:
a keeper circuit coupled to the enable circuit and further coupled between the input node and the output node.

9. The circuit of claim 7 , wherein the first means for driving comprises:
a NAND gate coupled to the enable circuit and including a first output node;
an output drive transistor coupled to the first output node of the NAND gate;
a rising edge delay circuit coupled to the first output node of the NAND gate and the enable circuit; and
a delay circuit coupled in parallel with a portion of the rising edge delay circuit.

10. The circuit of claim 9 , wherein the first means for driving further comprises:
a latch circuit coupled to the enable circuit, the NAND gate, and the rising edge delay circuit; and
a falling edge reset circuit coupled to the enable circuit and the second means for driving.

11. The circuit of claim 7 , wherein the second means for driving comprises:
a NOR gate coupled to the enable circuit and including a first output node;
an output drive transistor coupled to the first output node of the NOR gate;
a falling edge delay circuit coupled to the first output node of the NOR gate and the enable circuit; and
a delay circuit coupled in parallel with a portion of the falling edge delay circuit.

12. The circuit of claim 11 , wherein the second means for driving further comprises:
a latch circuit coupled to the enable circuit, the NOR gate, and the falling edge delay circuit; and
a rising edge reset circuit coupled to the enable circuit and the first means for driving.

13. A circuit, comprising:
an enable circuit operable to receive an enable signal;
an up drive circuit coupled to the enable circuit; and
a down drive circuit coupled to the enable circuit, wherein if the enable signal is in a first state, one of the up drive circuit or the down drive circuit is operable for a period of time to drive a signal that represents an input signal, wherein the period of time terminates independently of the input signal, and wherein if the enable signal is in a second state, the circuit is operable in an impedance state.

14. The circuit of claim 13 , further comprising:
a keeper circuit coupled to the enable circuit.

15. The circuit of claim 13 , wherein the up drive circuit comprises:
a NAND gate coupled to the enable circuit and including a first output node;
an output drive transistor coupled to the first output node of the NAND gate;
a rising edge delay circuit coupled to the first output node of the NAND gate and the enable circuit; and
a delay circuit coupled in parallel with a portion of the rising edge delay circuit.

16. The circuit of claim 15 , wherein the up drive circuit further comprises:
a latch circuit coupled to the enable circuit, the NAND gate, and the rising edge delay circuit; and
a falling edge reset circuit coupled to the enable circuit and the down drive circuit.

17. The circuit of claim 13 , wherein the down drive circuit comprises:
a NOR gate coupled to the enable circuit and including a first output node;
an output drive transistor coupled to the first output node of the NOR gate;
a falling edge delay circuit coupled to the first output node of the NOR gate and the enable circuit; and
a delay circuit coupled in parallel with a portion of the falling edge delay circuit.

18. The circuit of claim 17 , wherein the down drive circuit further comprises:
a latch circuit coupled to the enable circuit, the NOR gate, and the falling edge delay circuit; and
a rising edge reset circuit coupled to the enable circuit and the up drive circuit.

19. The circuit of claim 13 , further comprising:
an input node operable to receive the input signal.

20. The circuit of claim 13 , further comprising:
an output node operable to receive the signal.

Assignees

• Intellectual Ventures Holding 81 Llc

Inventors

• Masleid Robert P
• Pitkethly Scott

Classifications

• H03K17/002

  Switching arrangements with several input- or output terminals (code converters H03M5/00, H03M7/00) · CPC title

• H03K19/09429 Primary

  one of the states being the high impedance or floating state · CPC title