Three dimensional memory array architecture

Patent metadata

Field	Value
Publication number	US-9595667-B2
Application number	US-201615011816-A
Country	US
Kind code	B2
Filing date	Feb 1, 2016
Priority date	Aug 31, 2012
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension intersects a portion of at least one of the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension.

First claim

What is claimed is:

1. A three dimensional memory array, comprising:
a stack comprising a plurality of first conductive lines at a number of levels separated from one another by an insulation material;
a storage element material substantially perpendicular to the plurality of first conductive lines and the insulation material, wherein the storage element material is in direct contact with the insulation material but not in direct contact with the first conductive lines, wherein the plurality of first conductive lines are recessed, and wherein the storage element material is separated from a first recessed conductive line of the plurality of recessed first conductive lines by at least one of a cell select device material and an insulating material within the recess; and
a conductive extension material over the storage element material.

2. The three dimensional memory array of claim 1 , wherein the cell select device material comprises a discrete ring structure around the conductive extension and the storage element material.

3. The three dimensional memory array of claim 1 , wherein the storage element material is separated from the plurality of first conductive lines by an insulating material comprising a selectively oxidized portion of the plurality of first conductive lines.

4. The three dimensional memory array of claim 1 , wherein the conductive extension intersects a portion of at least one of the plurality of first conductive lines.

5. The three dimensional memory array of claim 1 , wherein the conductive extension is coupled to at least one of a plurality of second conductive lines extending substantially perpendicular to the plurality of first conductive lines.

6. The three dimensional memory array of claim 1 , wherein the plurality of first conductive lines at the number of levels are additionally separated from one another by a heater material.

7. The three dimensional memory array of claim 6 , wherein the storage element material is additionally in contact with the heater material.

8. The three dimensional memory array of claim 1 , wherein each of the plurality of first conductive lines comprises a pair of conductive lines with an interceding heating material between the pair of conductive lines.

9. A method of forming a memory array, comprising:
forming a stack comprising a plurality of first conductive lines separated from one another by insulation material;
forming a via through the stack;
forming a recess at each of the plurality of first conductive lines from a wall of the via;
forming an insulating material within the recess;
forming a storage element material within the via in direct contact with the insulation material but not in direct contact with the first conductive lines; and
forming a conductive extension over the storage element material within the via.

10. The method of claim 9 , wherein the plurality of first conductive lines are additionally separated from one another by a heater material and wherein the storage element material is in contact with the heater material.

11. The method of claim 9 , wherein each of the plurality of first conductive lines includes a pair of conductive lines with an interceding heater material in between.

12. A method of forming a memory array, comprising:
forming a stack comprising a plurality of first conductive lines at a number of levels separated from one another by at least an insulation material;
forming at least one conductive extension extending substantially perpendicular to and intersecting with at least one of the plurality of first conductive lines; and
forming a second conductive line over the plurality of first conductive lines and the at least one conductive extension; and
forming storage element material around the at least one conductive extension.

13. The method of claim 12 , further comprising forming a cell select material around at least a portion of the at least one conductive extension.

14. The method of claim 12 , wherein the plurality of first conductive lines are recessed.

15. A method of forming a memory array, comprising:
forming a stack comprising a plurality of first conductive lines separated from one another by insulation material;
forming a via through the stack;
forming a recess at each of the plurality of first conductive lines from a wall of the via;
forming a cell select device material within the recess;
forming a storage element material within the via in direct contact with the insulation material but not in direct contact with the first conductive lines; and
forming a conductive extension over the storage element material within the via,
wherein forming the cell select device material within the recess includes forming the cell select device material as a discrete ring structure around the conductive extension and the storage element material.

16. A three dimensional memory array, comprising:
a stack comprising a plurality of first conductive lines at a number of levels separated from one another by an insulation material;
a storage element material substantially perpendicular to the plurality of first conductive lines and the insulation material, wherein the storage element material is in direct contact with the insulation material but not in direct contact with the first conductive lines; and
a conductive extension material over the storage element material,
wherein each of the plurality of first conductive lines comprises a pair of conductive lines with an interceding heating material between the pair of conductive lines.

Assignees

• Micron Technology Inc

Inventors

• Pio Federico

Classifications

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D84/206

  of combinations of capacitors and resistors · CPC title

• H10D84/00 Primary

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• H01L27/224

  Electricity · mapped topic

• H01L45/06 Primary

  Electricity · mapped topic