Noise-shaping circuit, digital-to-time converter, analog-to-digital converter, digital-to-analog converter frequency synthesizer, transmitter, receiver, transceiver, method for shaping noise in an input signal

Patent metadata

Field	Value
Publication number	US-9590647-B2
Application number	US-201514856854-A
Country	US
Kind code	B2
Filing date	Sep 17, 2015
Priority date	Dec 23, 2014
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

A noise shaping circuit according to an example includes a forward signal path configured to generate an output signal based on an input signal, a feedback signal path configured to feed back a feedback signal based on the output signal to the forward signal path, and a dither generator configured to generate a dither signal and to couple the dither signal into the forward signal path to modify the input signal and into the feedback signal path. Employing a noise shaping circuit according to an example may improve an overall noise performance.

First claim

The invention claimed is:

1. A noise shaping circuit comprising:
a forward signal path configured to generate an output signal based on an input signal;
a feedback signal path configured to feed back a feedback signal based on the output signal to the forward signal path; and
a dither generator configured to generate a dither signal and to couple the dither signal into the forward signal path to modify the input signal and into the feedback signal path,
wherein the feedback signal path comprises a noise shaping filter configured to generate the feedback signal based on an error signal and to provide the feedback signal to the forward signal path, the error signal indicating a difference of the output signal with respect to an intended value, and
wherein the feedback signal path comprises a dither signal combiner configured to combine the error signal with the dither signal to provide a dithered error signal to the noise shaping filter.

2. The noise shaping circuit according to claim 1 , wherein the forward signal path further comprises a signal processing circuit configured to generate the output signal based on the input signal modified by the dither signal.

3. The noise shaping circuit according to claim 2 , wherein the feedback signal path comprises a subtractor coupled to an input of the signal processing circuit and an output of the forward signal path to receive the output signal and configured to generate the error signal based on a difference of the output signal and the signal provided to the signal processing circuit.

4. The noise shaping circuit according to claim 2 , wherein the signal processing circuit comprises a quantization circuit configured to modify a value of the signal provided to the quantization circuit.

5. The noise shaping circuit according to claim 2 , wherein the signal processing circuit is configured to at least one of re-quantizing the signal provided to the signal processing circuit, reducing the number of different values the output signal can acquire with respect to the number of different values of the signal provided to the signal processing circuit and at least partially compensating a non-linearity of a component coupled to the noise shaping circuit.

6. The noise shaping circuit according to claim 1 , wherein the forward signal path comprises a dither signal combiner coupled between an input and an output of the forward signal path to combine the dither signal with the signal provided to the dither signal combiner of the forward signal path.

7. The noise shaping circuit according to claim 6 , wherein the dither signal combiner of the feedback signal path and the dither signal combiner of the forward signal path are configured to combine the dither signal having the same phase relationship.

8. The noise shaping circuit according to claim 1 , wherein the noise shaping circuit is a digital noise shaping circuit, and wherein the forward signal path, the feedback signal path and the dither generator are configured to receive, process and provide signals comprising a sequence of digital values.

9. The noise shaping circuit according to claim 1 , wherein the dither generator is configured to generate the dither signal based at least on one of a random signal, a pseudo-random signal and a dither input signal.

10. The noise shaping circuit according claim 9 , wherein the dither generator is configured to generate the dither signal comprising a spectral density depending on the dither input signal.

11. The noise shaping circuit according claim 1 , wherein the dither generator is configured to generate the dither signal comprising at least one of a white noise spectral density, a pink-noise spectral density, a Brownian-noise spectral density and a high-pass filtered white-noise spectral density.

12. The noise shaping circuit according to claim 1 , wherein the dither generator comprises at least one of a random number generator, a pseudo-random number generator and a look-up-table to generate a random signal or a pseudo-random signal.

13. The noise shaping circuit according to claim 12 , wherein the dither generator further comprises a processing circuit configured to process the random signal or the pseudo-random signal.

14. The noise shaping circuit according to claim 13 , wherein the processing circuit of the dither generator is configured to at least one of high-pass filtering the random signal or the pseudo-random signal, differentiating the random signal or the pseudo-random signal and modifying a distribution of values of the random signal or the pseudo-random signal based on a dither input signal.

15. A noise shaping circuit comprising:
a forward signal path configured to generate an output signal based on an input signal;
a feedback signal path configured to feed back a feedback signal based on the output signal to the forward signal path; and
a dither generator configured to generate a dither signal and to couple the dither signal into the forward signal path to modify the input signal and into the feedback signal path,
wherein the forward signal path comprises a feedback combiner configured to modify the input signal by combing the input signal with the feedback signal, and
wherein the feedback combiner is configured to subtract the feedback signal from the input signal.

16. A digital-to-time converter comprising:
a noise shaping circuit comprising a forward signal path configured to generate an output signal based on an input signal, a feedback signal path configured to feed back a feedback signal based on the output signal to the forward signal path, and a dither generator configured to generate a dither signal and to couple the dither signal into the forward signal path to modify the input signal and into the feedback signal path, wherein the noise shaping circuit is configured to receive a control signal as the input signal; and
a digital-to-time converter circuit coupled to an output of the noise shaping circuit to receive the output signal from the noise shaping circuit as a modified control signal, wherein the digital-to-time converter circuit is configured to generate a processed oscillating signal by delaying a oscillating signal in response to the modified control signal,
wherein the feedback signal path comprises a dither signal combiner configured to combine the error signal with the dither signal to provide a dithered error signal to the noise shaping circuit.

17. The digital-to-time converter according to claim 16 , wherein the noise shaping circuit comprises a signal processing circuit configured to at least one of reducing a number of different states of the output signal compared to the signal provided to the signal processing circuit and compensating a non-linearity of the digital-to-time converter circuit fully or at least partially.

18. The digital-to-time converter according to claim 16 , wherein the digital-to-time converter is a digital digital-to-time converter.

Assignees

• Intel Ip Corp

Inventors

• Preyler Peter
• Mayer Thomas
• Tertinek Stefan

Classifications

• H03M3/436

  characterised by the order of the loop filter, e.g. error feedback type · CPC title

• H03L7/20 Primary

  using a harmonic phase-locked loop, i.e. a loop which can be locked to one of a number of harmonically related frequencies applied to it (H03L7/22 takes precedence) · CPC title

• H03M3/33 Primary

  the dither being a random signal · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title

• H03L7/16

  Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop · CPC title