Radiation-hardened dual gate semiconductor transistor devices containing various improved structures including MOSFET gate and JFET gate structures and related methods

Patent metadata

Field	Value
Publication number	US-9590611-B2
Application number	US-201514683438-A
Country	US
Kind code	B2
Filing date	Apr 10, 2015
Priority date	Apr 10, 2014
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

Systems and methods for controlling current or mitigating electromagnetic or radiation interference effects using structures configured to cooperatively control a common semi-conductive channel region (SCR). One embodiment includes providing a metal oxide semiconductor field effect transistor (MOSFET) section formed with an exemplary SCR and two junction field effect transistor (JFET) gates on opposing sides of the MOSFET's SCR such that operation of the JFET modulates or controls current through the MOSFET's. With two JFET gate terminals to modulate various embodiments' signal(s), an improved mixer, demodulator, and gain control element in, e.g., analog circuits can be realized. Additionally, a direct current (DC)-biased terminal of one embodiment decreases cross-talk with other devices. A lens structure can also be incorporated into MOSFET structures to further adjust operation of the MOSFET. An embodiment can also include a current leakage mitigation structure configured to reduce or eliminate current leakage between MOSFET and JFET structures.

First claim

The invention claimed is:

1. An electrical system comprising:
a first substrate section;
a metal oxide semi-conductor field effect transistor (MOSFET) section disposed in said first substrate section, said MOSFET section comprising a MOSFET section, a source region formed into said MOSFET section, a drain region formed inside said MOSFET section wherein the source region and drain region are formed on opposing sides of a semi-conductive channel region (SCR) formed in said first substrate section, a gate insulator region formed on one side of said MOSFET section adjacent to said SCR, and a control gate formed adjacent to a plane defined by said first SCR and in contact with said gate insulator region on an opposing side from a side of said gate insulator region facing said SCR; and
a first and second junction field effect transistor (JFET) section respectively disposed into said first substrate section on opposing sides of said SCR.

2. An electrical system as in claim 1 , wherein said insulator layer comprises a lens shape section formed with a shape thicker in a center section of said lens shape section along a drain-source axis, operable to shape an electric field action of the MOS gate to be less strong in a center section of the drain-source axis.

3. An electrical system as in claim 1 , further comprising a current leakage mitigation structure (CLMS) formed as a semi-conductive doped material in said first substrate on a same plane as said SCR and having a first and second CLMS section respectively disposed adjacent to and between said source and drain structures, said CLMS is formed with a semi-conductive dopant having a greater concentration than a same-type semi-conductive dopant within said first substrate that has an effect of directing charge away from said drain terminal from said first or second JFET sections so as to at least partially electrically isolate said first and second JFET sections from said drain, said CLMS is also formed with a CLMS contact formed to receive an external electrical voltage or bias to said CLMS.

4. A mixer system comprising:
a semiconductor device comprising:
a first substrate section;
a metal oxide semi-conductor field effect transistor (MOSFET) section disposed in said first substrate section, said MOSFET section comprising a MOSFET section, a source region formed into said MOSFET section, a drain region formed inside said MOSFET section wherein the source region and drain region are formed on opposing sides of a semi-conductive channel region (SCR) formed in said first substrate section, a gate insulator region formed on one side of said MOSFET section adjacent to said SCR, and a control gate formed adjacent to a plane defined by said SCR and in contact with said gate insulator region on an opposing side from a side of said gate insulator region facing said SCR; and
a first and second junction field effect transistor (JFET) section respectively disposed into said first substrate section on opposing sides of said SCR;

a mixer section coupled to the semi-conductive device comprising a radio frequency mixer section configured for modulation and demodulation of encoded signals passed into said semi-conductive device.

5. A system as in claim 4 , wherein said insulator layer comprises a lens shape section formed with a shape thicker in a center section of said lens shape section along a drain-source axis, operable to shape an electric field action of the MOS gate to be less strong in a center section of the drain-source axis.

6. An electrical system as in claim 4 , further comprising a current leakage mitigation structure (CLMS) formed as a semi-conductive doped material in said first substrate on a same plane as said SCR and having a first and second CLMS section respectively disposed adjacent to and between said source and drain structures, said CLMS is formed with a semi-conductive dopant having a greater concentration than a same-type semi-conductive dopant within said first substrate that has an effect of directing charge away from said drain terminal from said first or second JFET sections so as to at least partially electrically isolate said first and second JFET sections from said drain, said CLMS is also formed with a CLMS contact formed to receive an external electrical voltage or bias to said CLMS.

7. An automatic gain control system comprising:
a semiconductor device comprising
a first substrate section;
a metal oxide semi-conductor field effect transistor (MOSFET) section disposed in said first substrate section, said MOSFET section comprising a MOSFET section, a source region formed into said MOSFET section, a drain region formed inside said MOSFET section wherein the source region and drain region are formed on opposing sides of a semi-conductive channel region (SCR) formed in said first substrate section, a gate insulator region formed on one side of said MOSFET section adjacent to said SCR, and a control gate formed adjacent to a plane defined by said SCR and in contact with said gate insulator region on an opposing side from a side of said gate insulator region facing said SCR; and
a first and second junction field effect transistor (JFET) section respectively disposed into said first substrate section disposed on opposing sides of said SCR;

an automatic gain control section coupled to the semi-conductive device comprising an amplifier section configured with automatic gain control for signals input into said semi-conductive device.

8. A system as in claim 7 , wherein said insulator layer comprises a lens shape section formed with a shape thicker in a center section of said lens shape section along a drain-source axis, operable to shape an electric field action of the MOS gate to be less strong in a center section of the drain-source axis.

9. An electrical system as in claim 7 , further comprising a current leakage mitigation structure (CLMS) formed as a semi-conductive doped material in said first substrate on a same plane as said SCR and having a first and second CLMS section respectively disposed adjacent to and between said source and drain structures, said CLMS is formed with a semi-conductive dopant having a greater concentration than a same-type semi-conductive dopant within said first substrate that has an effect of directing charge away from said drain terminal from said first or second JFET sections so as to at least partially electrically isolate said first and second JFET sections from said drain, said CLMS is also formed with a CLMS contact formed to receive an external electrical voltage or bias to said CLMS.

10. An electrical system with radiation responsive, measurement, or mitigation systems comprising:
a semi-conductive device comprising:
a first substrate section;
a metal oxide semi-conductor field effect transistor (MOSFET) section disposed in said first substrate section, said MOSFET section comprising a MOSFET section, a source region formed into said MOSFET section, a drain region formed inside said MOSFET section wherein the source region and drain region are formed on opposing sides of a semi-conductive channel region (SCR) formed in said first substrate section, a gate insulator region formed on one side of said MOSFET section adjacent to said SCR, and a control gate formed adjacent to a plane defined by said SCR and in contact with said gate insulator region on an opposing side from a side of said gate insulator region facing said SCR; and
a first and second junction field effect transistor (JFET) section respectively disposed into said first substrate section disposed on opposing sides of said SCR;

a control system comprising a plurality of sections including a first section for measuring current passed through said MOSFET, perform

Assignees

• Us Navy

Inventors

• Cole Patrick L
• Duncan Adam R

Classifications

• H10D84/80

  characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence) · CPC title

• H01L29/66484

  Electricity · mapped topic

• H01L29/42368

  Electricity · mapped topic

• H01L21/823412

  Electricity · mapped topic

• H01L29/808

  Electricity · mapped topic