Driver circuit for signal transmission and control method of driver circuit

US9590610B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9590610-B2
Application numberUS-201514822913-A
CountryUS
Kind codeB2
Filing dateAug 11, 2015
Priority dateDec 30, 2014
Publication dateMar 7, 2017
Grant dateMar 7, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A driver circuit for receiving input data and generating an output signal to a termination element is disclosed, wherein the input data has a first bit and second bit, and the driver circuit includes: a pair of differential output terminals, arranged for outputting the output signal, wherein the pair of differential output terminals has a first output terminal and a second output terminal; a current mode drive unit, coupled to the pair of differential output terminals, for outputting a current from one of the first output terminal and the second output terminal, and receiving the current from the other of the first output terminal and the second output terminal according to the first bit; and a voltage mode drive unit, coupled to the pair of differential output terminals, for providing voltages to the first output terminal and the second output terminal according to at least the second bit.

First claim

Opening claim text (preview).

What is claimed is: 1. A driver circuit for receiving input data and generating an output signal to a termination element, wherein when the driver circuit operates as a first mode, the input data has a first bit and second bit, one of the first bit and the second bit is a most significant bit (MSB), and the other one of the first bit and the second bit is a least significant bit (LSB) and the driver circuit comprises: a pair of differential output terminals, arranged for outputting the output signal, wherein the pair of differential output terminals has a first output terminal and a second output terminal; a first current mode drive unit, coupled to the pair of differential output terminals, for outputting a current from one of the first output terminal and the second output terminal, and receiving the current from the other of the first output terminal and the second output terminal according to the first bit; and a voltage mode drive unit, coupled to the pair of differential output terminals, for providing voltages to the first output terminal and the second output terminal according to at least the second bit. 2. The driver circuit of claim 1 , wherein the first current mode drive unit comprises: a current source; a current sink; and a switch module, coupled between the current source and the pair of differential output terminals, and coupled between the current sink and the pair of differential output terminals; wherein the current source is coupled to one of the first output terminal and the second output terminal via the switch module according to the first bit, and the current sink is coupled to the other one of the first output terminal and the second output terminal via the switch module according to the first bit. 3. The driver circuit of claim 1 , wherein the voltage mode drive unit comprises: a first voltage source, for providing a first reference voltage; a second voltage source, for providing a second reference voltage; and a switch module, coupled between the first voltage source and the pair of differential output terminals, and coupled between the second voltage source and the pair of differential output terminals; wherein the first voltage source is coupled to one of the first output terminal and the second output terminal via the switch module according to the second bit, and the second voltage source is coupled to the other one of the first output terminal and the second output terminal via the switch module according to the second bit. 4. The driver circuit of claim 3 , wherein the first voltage mode drive unit further comprises: a first impedance element, coupled between the first voltage source and the first output terminal; a second impedance element, coupled between the first voltage source and the second output terminal; a third impedance element, coupled between the second voltage source and the first output terminal; and a fourth impedance element, coupled between the second voltage source and the second output terminal; wherein the first impedance element, the second impedance element, the third impedance element and the fourth impedance element have the same resistance. 5. The driver circuit of claim 1 , further comprising: a second current mode drive unit, coupled to the pair of differential output terminals; wherein the first current mode drive unit and the second current mode drive unit are arranged for outputting the current from one of the first output terminal and the second output terminal, and receiving the current from the other of the first output terminal and the second output terminal according to the first bit and the second bit. 6. The driver circuit of claim 5 , wherein the first current mode drive unit comprises: a first current source; a first current sink; and a first switch module, coupled between the first current source and the pair of differential output terminals, and coupled between the first current sink and the pair of differential output terminals; and the second current mode drive unit comprises: a second current source; a second current sink; and a second switch module, coupled between the second current source and the pair of differential output terminals, and coupled between the second current sink and the pair of differential output terminals; wherein the first current source is coupled to one of the first output terminal and the second output terminal via the first switch module according to the second bit, and the first current sink is coupled to the other one of the first output terminal and the second output terminal via the first switch module according to the second bit; and the second current source is coupled to one of the first output terminal and the second output terminal via the second switch module according to the first bit, and the second current sink is coupled to the other one of the first output terminal and the second output terminal via the second switch module according to the first bit. 7. The driver circuit of claim 6 , wherein a current provided by the first current source is twice that of the second current source. 8. The driver circuit of claim 1 , wherein the voltage mode drive unit provides the voltages to the first output terminal and the second output terminal according to both the first bit and the second bit. 9. The driver circuit of claim 8 , wherein the voltage mode drive unit comprises: a first voltage source, for providing a first reference voltage; a second voltage source, for providing a second reference voltage; a switch module, coupled between the first voltage source and the pair of differential output terminals, and coupled between the second voltage source and the pair of differential output terminals; a first impedance circuit module, coupled between the switch module and the first output terminal; and a second impedance circuit module, coupled between the switch module and the second output terminal. 10. The driver circuit of claim 9 , wherein the first impedance circuit module comprises: a first impedance element, coupled between the first voltage source and the first output terminal; a second impedance element, coupled between the first voltage source and the first output terminal; a third impedance element, coupled between the second voltage source and the first output terminal; and a fourth impedance element, coupled between the second voltage source and the first output terminal; and the second impedance circuit module comprises: a fifth impedance element, coupled between the first voltage source and the second output terminal; a sixth impedance element, coupled between the first voltage source and the second output terminal; a seventh impedance element, coupled between the second voltage source and the second output terminal; and an eighth impedance element, coupled between the second voltage source and the second output terminal. 11. The driver circuit of claim 10 , wherein the first voltage source is selectively coupled to the first impedance element or the fifth impedance element according to the second bit, the first voltage source is selectively coupled to the second impedance element or the sixth impedance element according to the first bit, the second voltage source is selectively coupled to the third impedance element or the seventh impedance element according to the second bit, and the second voltage source is selectively coupled to the fourth impedance element or the eighth impedance element according to the first bit. 12. The driver circuit of claim 10 , wherein the first impedance element and the third impedance element have the same resistance, and the second impedance element and the fourt

Assignees

Inventors

Classifications

  • Provision for current-mode coupling · CPC title

  • Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

  • H03K17/10Primary

    Modifications for increasing the maximum permissible switched voltage · CPC title

  • using binary codes · CPC title

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Frequently asked questions

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What does patent US9590610B2 cover?
A driver circuit for receiving input data and generating an output signal to a termination element is disclosed, wherein the input data has a first bit and second bit, and the driver circuit includes: a pair of differential output terminals, arranged for outputting the output signal, wherein the pair of differential output terminals has a first output terminal and a second output terminal; a cu…
Who is the assignee on this patent?
Mediatek Inc
What technology area does this patent fall under?
Primary CPC classification H04L25/0272. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 07 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).