Semiconductor device with power transistor cells and lateral transistors and method of manufacturing

Patent metadata

Field	Value
Publication number	US-9590094-B2
Application number	US-201514738245-A
Country	US
Kind code	B2
Filing date	Jun 12, 2015
Priority date	Jun 26, 2014
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

By thermal oxidation a field oxide layer is formed that lines first and second trenches that extend from a main surface into a semiconductor layer. After the thermal oxidation, field electrodes and trench gate electrodes of power transistor cells are formed in the first and second trenches. A protection cover including a silicon nitride layer is formed that covers a cell area with the first and second trenches. With the protection cover covering the cell area, planar gate electrodes of lateral transistors are formed in a support area of the semiconductor layer.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming, by thermal oxidation, a field oxide layer lining first and second trenches that extend from a main surface into a semiconductor layer;
forming, after the thermal oxidation, field electrodes and trench gate electrodes of power transistor cells in the first and second trenches;
forming a protection cover comprising a silicon nitride layer and covering a cell area that comprises the first and second trenches;
forming, by local oxidation of silicon and after forming the protection cover, insulator structures between the cell area and the support area and/or between areas assigned to lateral transistors; and
forming planar gate electrodes of lateral transistors in a support area of the semiconductor layer with the protection cover covering the cell area.

2. The method of claim 1 , further comprising:
implanting, after forming the planar gate electrodes, dopants for contemporaneously forming source zones of the power transistor cells and source/drain zones of the lateral transistors.

3. The method of claim 2 , wherein
the source zones and the source/drain zones have a same vertical extension with respect to the main surface.

4. The method of claim 1 , wherein
the local oxidation of silicon uses an oxidation mask comprising a silicon nitride layer, and
the insulator structures are formed in openings of the oxidation mask.

5. The method of claim 4 , further comprising:
removing the oxidation mask; and
removing nitrogen-containing portions by a wet oxidation after providing the protection cover, wherein an auxiliary oxide layer is formed.

6. The method of claim 5 , further comprising:
replacing the auxiliary oxide layer by a planar gate dielectric for the lateral transistors.

7. The method of claim 1 , further comprising:
forming and recessing, before forming the field oxide layer, a sacrificial oxide lining the first and second trenches.

8. The method of claim 1 , further comprising:
implanting, after forming the planar gate electrodes, dopants for forming body zones of the power transistor cells and wells of the second conductivity type in a support area outside the cell area.

9. A method of manufacturing a semiconductor device, the method comprising:
forming, by thermal oxidation, a field oxide layer lining first and second trenches that extend from a main surface into a semiconductor layer;
forming, after the thermal oxidation, field electrodes and trench gate electrodes of power transistor cells in the first and second trenches, wherein forming the field electrodes comprises depositing a conductive first fill material, removing first portions of the first fill material in a polishing process and removing second portions in upper sections of the first trenches by a recess etch, wherein remnant portions of the first fill material form the field electrodes;
removing a first portion of the field oxide layer in the upper sections of the first trenches by using the field electrodes as etch mask;
forming a gate dielectric on portions of the semiconductor layer exposed by removing the first portion of the field oxide layer;
forming a protection cover comprising a silicon nitride layer and covering a cell area that comprises the first and second trenches; and
forming planar gate electrodes of lateral transistors in a support area of the semiconductor layer with the protection cover covering the cell area.

10. The method of claim 9 , wherein
forming the trench gate electrodes comprises depositing a conductive second fill material and removing first portions of the second fill material in a polishing process to form trench gate electrodes in the upper sections of the first trenches.

Assignees

• Infineon Technologies Ag

Inventors

• Zink Robert
• Decker Stefan
• Lanzerstorfer Sven

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6322

  Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

• H10P14/6304

  Formation by oxidation, e.g. oxidation of the substrate · CPC title