Semiconductor package including stepwise stacked chips

Patent metadata

Field	Value
Publication number	US-9589930-B2
Application number	US-201414588243-A
Country	US
Kind code	B2
Filing date	Dec 31, 2014
Priority date	Jan 16, 2014
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

A semiconductor package comprises a package substrate; a first chip stack and a second chip stack mounted side by side on the package substrate, wherein the first and second chip stacks each include a plurality of semiconductor chips stacked on the package substrate, wherein each of the semiconductor chips includes a plurality of bonding pads provided on a respective edge region thereof, wherein at least some of the plurality of bonding pads are functional pads, and wherein the functional pads occupy a region that is substantially less than an entirety of the respective edge region.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a first chip stack and a second chip stack mounted side by side on a package substrate and each connected to the package substrate in a wire bonding manner,
wherein the first chip stack comprises a plurality of first semiconductor chips that are stepwise stacked on the package substrate to have a descending staircase structure from the first chip stack toward the second chip stack,
wherein the second chip stack comprises a plurality of second semiconductor chips that are stepwise stacked on the package substrate to have a descending staircase structure from the second chip stack toward the first chip stack,
wherein the first semiconductor chips comprise bonding pads on first edge regions of the top surfaces of thereof, respectively,
wherein the top surfaces of first semiconductor chips include second edge regions, respectively, wherein the second edge regions of the first semiconductor chips comprise no bonding pads,
wherein the first edge regions of the first semiconductor chips are aligned with a first virtual line in a plan view,
wherein the second semiconductor chips comprise bonding pads, respectively, and
wherein the bonding pads of second the semiconductor chips are not aligned with the first virtual line in a plan view.

2. The package of claim 1 , further comprising a third chip disposed on the package substrate between the first chip stack and the second chip stack.

3. The package of claim 1 , wherein the first chip stack and the second chip stack are connected to the package substrate via bonding wires.

4. The package of claim 1 , the bonding pads of the second semiconductor chips are aligned with a second virtual line in a plan view,
wherein the second virtual line is offset from first virtual line in a first direction, wherein the first direction intersects the first and second virtual lines in a plan view.

5. The package of claim 4 , wherein the second edge regions of the first semiconductor chips are aligned with the second virtual line in a plan view.

6. The package of claim 1 , one of the second edge regions corresponding one of the first semiconductor chips is not covered by others of the first semiconductor chips.

7. A semiconductor package, comprising:
a package substrate; and
a first chip stack and a second chip stack mounted side by side on the package substrate and connected to the package substrate via bonding wires, the first chip stack comprising a first edge and the second chip stack comprising a first edge, the first edge of the first chip stack being next to the first edge of the second chip stack,
wherein the first and second chip stacks each include a plurality of semiconductor chips stacked on the package substrate, the first and second chip stacks each having a staircase structure that extends away from the first edge of the first chip stack and away from the first edge of the second chip stack,
wherein the semiconductor chips include bonding pad groups provided on chip edge regions of top surfaces thereof that are next to the first edges of the first and second chip stacks,
wherein each of the bonding pad groups includes at least one of bonding pads,
wherein the bonding pad groups of the semiconductor chips of the first chip stack are aligned with a first virtual line in a plan view,
the bonding pad groups of the semiconductor chips of the second chip stack are aligned with a second virtual line in a plan view, wherein the bonding pad groups of the semiconductor chips of the second chip stack are not aligned with the first virtual line, and
wherein the first virtual line is offset from the second virtual line in a plan view.

8. A semiconductor package, comprising:
a package substrate; and
a first chip stack and a second chip stack mounted side by side on the package substrate, the first chip stack comprising a first edge that corresponds to and is next to a second edge of the second chip stack,
wherein the first chip stack includes a plurality of first semiconductor chips, each of the first semiconductor chips comprising a first chip edge region that is next to and corresponds to the first edge of the first chip stack, the first chip edge region of each first semiconductor chip comprising a first end and a second end that is opposite to the first end, the first end of the first chip edge region of each first semiconductor chip corresponding to the first end of the first chip edge region of another one of the first semiconductor chips and the second end of the first chip edge region of each first semiconductor chip corresponding to the second end of the first chip edge region of another one of the first semiconductor chips, the first semiconductor chips each including a plurality of first bonding pads arranged in a first region along the first edge thereof, the first region extending from the first end of the first chip edge region substantially less than an entirety of the first chip edge region thereof, and a second region of the first chip edge region extending from the second end of the first chip edge region thereof, both the first region and the second region being immediately next to the first edge, the first region being immediately next to the second region along the first edge between the first end and the second end of the first chip edge region, and the second region comprising no bonding pads, and
wherein the second chip stack includes a plurality of second semiconductor chips, each of the second semiconductor chips comprising a second chip edge region that is next to and corresponds to the second edge of the second chip stack, the second chip edge region of each second semiconductor chip comprising a third end and a fourth end that is opposite to the third end, the third end of the second chip edge region of each second semiconductor chip corresponding to the third end of the second chip edge region of other second semiconductor chips and corresponding to the second end of the first chip edge region of the first semiconductor chips and the fourth end of the second chip edge region of each second semiconductor chip corresponding to the fourth end of the second chip edge region of the other second semiconductor chips and corresponding to the first end of the first chip edge region of the first semiconductor chips, the second semiconductor chips each including a plurality of second bonding pads arranged in a third region along the second chip edge region thereof, the third region extending from the third end of the second chip edge region thereof substantially less than an entirety of the second chip edge region, and a fourth region of the second chip edge region extending from the fourth end of the second chip edge region thereof, both the third region and the fourth region being immediately next to the second chip edge region, the third region being immediately adjacent to the fourth region along the second chip edge region, and the fourth region comprising no bonding pads,
wherein the first region of each first semiconductor chip overlaps with a first virtual line in a plan view,
wherein the second region of each first semiconductor chip is overlaps with a second virtual line in a plan view, and
wherein the first virtual line is substantially parallel to the second virtual line in a plan view.

9. The package of claim 8 , further comprising one or more third semiconductor chips mounted on the package substrate between the first chip stack and the second chip stack to be electrically coupled to at least one of the first and second chip stacks.

10. The package of claim 9 , wherein the one or more third chips are aligned with each other between the first and second chip stacks.

11

Assignees

• Park Chul
• Kim Kilsoo
• Lee In
• Samsung Electronics Co Ltd

Inventors

• Park Chul
• Kim Kilsoo
• Lee In

Classifications

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/271

  the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title