Electroless metal deposition on a manganese or manganese nitride barrier

Patent metadata

Field	Value
Publication number	US-9589896-B2
Application number	US-201615067033-A
Country	US
Kind code	B2
Filing date	Mar 10, 2016
Priority date	Mar 13, 2015
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

An electronic circuit structure comprising a substrate, a dielectric layer on top of the substrate and comprising a cavity having side-walls, a manganese or manganese nitride layer covering the side-walls, and a self-assembled monolayer, comprising an organic compound of formula Z-L-A, covering the manganese or manganese nitride layer, wherein Z is selected from the list consisting of a primary amino group, a carboxylic acid group, a thiol group, a selenol group and a heterocyclic group having an unsubstituted tertiary amine in the cycle, wherein L is an organic linker comprising from 1 to 12 carbon atoms and from 0 to 3 heteroatoms, and wherein A is a group attaching the linker to the manganese or manganese nitride layer.

First claim

What is claimed is:

1. An electronic circuit structure, comprising
a substrate;
a dielectric layer on top of the substrate, the dielectric layer comprising a cavity having side-walls;
a manganese or manganese nitride layer covering the side-walls; and
a self-assembled monolayer comprising an organic compound of formula Z-L-A, covering the manganese or manganese nitride layer, wherein Z is selected from the group consisting of a primary amino group, a carboxylic acid group, a thiol group, a selenol group, and a heterocyclic group having an unsubstituted tertiary amine in the cycle, wherein L is an organic linker having from 1 to 12 carbon atoms and from 0 to 3 heteroatoms, and wherein A is a group attaching the linker to the manganese or manganese nitride layer.

2. The electronic circuit structure of claim 1 , wherein the substrate has a conductive element at a surface thereof and wherein the cavity exposes at least part of the conductive element.

3. The electronic circuit structure of claim 1 , wherein the organic linker L has from 1 to 3 functional groups selected from the group consisting of primary amino groups and secondary amino groups.

4. The electronic circuit structure of claim 1 , further comprising one or more metal layers provided on the self-assembled monolayer.

5. The electronic circuit structure of claim 4 , wherein one of the one or more metal layers is a Pd layer provided on the self-assembled monolayer.

6. The electronic circuit structure of claim 5 , wherein one of the one or more metal layers is a cobalt-comprising or nickel-comprising layer deposited on the Pd layer.

7. The electronic circuit structure of claim 4 , wherein one of the one or more metal layers is a cobalt-comprising or nickel-comprising layer deposited on the self-assembled monolayer in an absence of a Pd layer.

8. The electronic circuit structure of claim 1 , wherein one of the one or more metal layers is a Cu layer deposited on a member of the group consisting of:
a cobalt-comprising or nickel-comprising layer;
a Pd layer; and
the self-assembled monolayer, in an absence of a cobalt-comprising layer, a nickel-comprising layer, and a Pd layer.

9. The electronic circuit structure of claim 1 , comprising a portion of a semiconductor device.

10. A process for manufacturing an electronic circuit structure, comprising:
providing a dielectric layer on top of a substrate, wherein the dielectric layer comprises a cavity having side-walls;
covering the side-walls with a manganese or manganese nitride layer; and
covering the manganese or manganese nitride layer with a self-assembled monolayer comprising an organic compound of formula Z-L-A′, wherein Z is selected from the group consisting of a primary amino group, a carboxylic acid group, a thiol group, a selenol group, and a heterocyclic group having an unsubstituted tertiary amine in the cycle, wherein L is an organic linker having from 1 to 12 carbon atoms and from 0 to 3 heteroatoms, and wherein A′ is a group configured for attaching the linker to the manganese or manganese nitride layer, whereby the electronic circuit structure of claim 1 is obtained.

11. The process of claim 10 , further comprising:
providing a Pd layer on the self-assembled monolayer;
depositing a cobalt-comprising or nickel-comprising layer on the Pd layer; and
depositing Cu on the cobalt-comprising or nickel-comprising layer.

12. The process of claim 10 , further comprising:
depositing a cobalt- or nickel-comprising layer on the self-assembled monolayer; and
depositing Cu on the cobalt-comprising or nickel-comprising layer, in an absence of a Pd layer.

13. The process of claim 10 , further comprising:
depositing Cu on the self-assembled monolayer in an absence of a cobalt-comprising layer, a nickel-comprising layer, and a Pd layer.

14. The process of claim 11 , wherein providing a Pd layer on the self-assembled monolayer comprises contacting the self-assembled monolayer with a Pd 2+ solution or with a liquid medium comprising Pd° nanoparticles.

15. The process of claim 11 , wherein at least one of depositing a cobalt-comprising or nickel-comprising layer or depositing Cu is performed by electroless deposition.

16. The process of claim 10 , wherein A′ is selected from the group consisting of SiX 3 groups and PO 3 H 2 groups, wherein each X is independently selected from the group consisting of H, Cl, O—CH 3 , O—C 2 H 5 , and O—C 3 H 7 .

17. The process of claim 10 , wherein the substrate comprises a conductive element at a surface thereof and wherein the cavity exposes at least part of the conductive element.

18. The process of claim 17 , further comprising:
providing a sacrificial protective layer on the exposed part of the conductive element prior to covering the manganese or manganese nitride layer with the self-assembled monolayer;
removing the sacrificial protective layer after covering the manganese or manganese nitride layer with the self-assembled monolayer; and
filling the cavity with one or more metal layers.

Assignees

• Imec Vzw

Inventors

• Armini Silvia

Classifications

• H10W20/0523

  by irradiating with ultraviolet or particle radiation · CPC title

• H10W20/044

  for electroless plating · CPC title

• H10W20/036

  the barrier, adhesion or liner layers being within a main fill metal · CPC title

• H10W20/035

  combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers · CPC title

• H10W20/034

  bottomless barrier, adhesion or liner layers · CPC title