Integrated dual power converter package having internal driver IC

Patent metadata

Field	Value
Publication number	US-9589872-B2
Application number	US-201313759734-A
Country	US
Kind code	B2
Filing date	Feb 5, 2013
Priority date	Mar 28, 2012
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

An integrated dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a driver integrated circuit (IC) paddle configured to support a driver IC for controlling each of the control FETs and each of the sync FETs. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively.

First claim

The invention claimed is:

1. An integrated dual power converter package comprising:
a leadframe comprising:
a first control FET paddle supporting a drain of a first control FET;
a second control FET paddle supporting a drain of a second control FET;
a sync FET paddle supporting a source of a first sync FET and a source of a second sync FET;
a source of said first control FET and a drain of said first sync FET having disposed thereon a first trace, connector, clip, ribbon, or wire;
a first switched node electrically connected to said source of said first control FET and said drain of said first sync FET;
a driver integrated circuit (IC) paddle supporting a driver IC for controlling each of said first and second control FETs and each of said first and second sync FETs.

2. The package of claim 1 , further comprising a second switched node electrically connected to a source of said second control FET and a drain of said second sync FET via a second trace, connector, clip, ribbon, or wire.

3. The package of claim 1 , wherein said first control FET paddle and said second control FET paddle are disposed substantially symmetrically on said leadframe with respect to said driver IC paddle.

4. The package of claim 1 , wherein said leadframe further comprises a first supply voltage contact configured for externally receiving a first supply voltage.

5. The package of claim 4 , wherein said leadframe further comprises a second supply voltage contact configured for externally receiving a second supply voltage.

6. The package of claim 1 , wherein said leadframe further comprises a ground contact for externally receiving a ground connection.

7. The package of claim 2 , wherein said leadframe further comprises a first output voltage contact configured to provide a first output voltage from said first switched node.

8. The package of claim 7 , wherein said leadframe further comprises a second output voltage contact configured to provide a second output voltage from said second switched node.

9. An integrated dual power converter package comprising:
a leadframe comprising:
a first control FET disposed on a first control FET paddle;
a second control FET disposed on a second control FET paddle;
a first sync FET and a second sync FET, each disposed on a sync FET paddle;
a source of said first control FET and a drain of said first sync FET having disposed thereon a first trace, connector, clip, ribbon, or wire;
a first switched node electrically connected to said source of said first control FET and said drain of said first sync FET;
a driver integrated circuit (IC) disposed on a driver IC paddle and configured to control said first and second control FETs and said first and second sync FETs.

10. The package of claim 9 , wherein said leadframe further comprises a second switched node electrically connected to a source of said second control FET and a drain of said second sync FET via a second trace, connector, clip, ribbon, or wire.

11. The package of claim 9 , wherein:
said first control FET is connected to a first supply voltage through said first control FET paddle;
said second control FET is connected to a second supply voltage through said second control FET paddle.

12. The package of claim 9 , wherein said first sync FET and said second sync FET are connected to ground through said sync FET paddle.

13. The package of claim 9 , wherein said first control FET and said first sync FET form a first half-bridge circuit and said second control FET and said second sync FET form a second half-bridge circuit.

14. The package of claim 9 , wherein said driver IC is configured to sense a current through said first control FET and/or a current through said second control FET.

15. The package of claim 10 , wherein said leadframe further comprises:
a first output voltage contact configured to provide a first output voltage from said first-switched node;
a second output voltage contact configured to provide a second output voltage from said second switched node.

Assignees

• Infineon Technologies Americas Corp

Inventors

• Cho Eung San
• Clavette Dan

Classifications

• H10W90/763

  between laterally-adjacent chips · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W90/811

  Multiple chips on leadframes · CPC title