Semiconductor package structure and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9589871-B2
Application number	US-201514685529-A
Country	US
Kind code	B2
Filing date	Apr 13, 2015
Priority date	Apr 13, 2015
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

The present disclosure relates to a semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes a leadframe and a semiconductor die. The leadframe includes a main portion and a protrusion portion. The semiconductor die is bonded to a first surface of the main portion. The protrusion portion protrudes from a second surface of the main portion. The position of the protrusion portion corresponds to the position of the semiconductor die.

First claim

What is claimed is:

1. A semiconductor package structure, comprising:
a leadframe comprising:
a main portion having a first surface and a second surface; and
a protrusion portion protruding from the second surface of the main portion;

a semiconductor die bonded to the main portion, wherein a position of the protrusion portion corresponds to a position of the semiconductor die and the protrusion portion protrudes from the second surface of the main portion below the die;
a first insulator covering the semiconductor die and a portion of the first surface of the main portion; and
a conductive pattern disposed on the first insulator and electrically connected to the semiconductor die.

2. The semiconductor package structure according to claim 1 , wherein the semiconductor die is bonded to the main portion by eutectic bonding.

3. The semiconductor package structure according to claim 1 , further comprising a second insulator covering a portion of the second surface of the main portion, wherein the protrusion portion is exposed from the second insulator.

4. The semiconductor package structure according to claim 3 , wherein the first insulator and the second insulator are formed of the same material.

5. The semiconductor package structure according to claim 3 , further comprising a metal layer covering the second insulator and the protrusion portion.

6. The semiconductor package structure according to claim 1 , wherein the main portion and the protrusion portion are integrally formed.

7. The semiconductor package structure according to claim 1 , wherein the protrusion portion is plated on the main portion.

8. The semiconductor package structure according to claim 1 , wherein the protrusion portion is a pattern selected from a group consisting of a plurality of parallel strips, a plurality of parallel strips within a frame, a plurality of crossed strips, a plurality of crossed strips within a frame, two strips perpendicular to one another, two strips intersecting each other, a plurality of dots arranged in an array, a spiral strip, a snake-shaped strip, a diamond, a plurality of squares, a plurality of circles connecting with strips, and a circle.

9. The semiconductor package structure according to claim 1 , wherein the main portion defines a cavity recessed below the first surface thereof, and the semiconductor die is disposed in the cavity.

10. A semiconductor package structure, comprising:
a leadframe having a first thickness at a first position and a second thickness at a second position, wherein the first position is different from the second position, and the first thickness is greater than the second thickness;
a semiconductor die bonded to the leadframe at a first surface of the leadframe, wherein the first position corresponds to a position of the semiconductor die, and the first position is below the semiconductor die at a second surface of the leadframe opposite the first surface;
a first insulator covering the semiconductor die and a portion of the first surface of the leadframe; and
a conductive pattern disposed on the first insulator and electrically connected to the semiconductor die.

11. The semiconductor package structure according to claim 10 , wherein the semiconductor die is bonded to the leadframe by eutectic bonding.

12. The semiconductor package structure according to claim 10 , further comprising a second insulator covering a portion of the second surface of the leadframe, wherein a portion of the leadframe is exposed from the second insulator.

13. The semiconductor package structure according to claim 10 , wherein the leadframe defines a cavity, and the semiconductor die is disposed in the cavity.

14. The semiconductor package structure according to claim 1 , wherein the protrusion portion is a plurality of parallel strips.

Assignees

• Advanced Semiconductor Eng

Inventors

• Chen Tang-Yuan
• Kao Chin-Li
• Chen Kuo-Hua
• Chen Ming-Hung
• Chen Dao-Long

Classifications

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/9413

  on encapsulations · CPC title