Substrate with embedded sintered heat spreader and process for making the same

US9589864B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9589864-B2
Application numberUS-201514937550-A
CountryUS
Kind codeB2
Filing dateNov 10, 2015
Priority dateMay 14, 2015
Publication dateMar 7, 2017
Grant dateMar 7, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure relates to a substrate with an embedded sintered heat spreader and a process for making the same. According to an exemplary process, at least one cavity is created through the substrate. Sinterable paste including metal particulates and binder material is then dispensed into the at least one cavity. Next, the sinterable paste is sintered to create a sintered heat spreader, which is characterized by high thermal conductivity. The sintered heat spreader adheres to the inside walls of the at least one cavity, enhancing the overall thermal conductivity of the substrate.

First claim

Opening claim text (preview).

What is claimed is: 1. A method comprising: providing a substrate having a top surface and a bottom surface opposite the top surface; creating at least one cavity that extends through the substrate from the top surface of the substrate to the bottom surface of the substrate; dispensing sinterable paste into the at least one cavity, wherein the sinterable paste comprises metal particulates with sub-nano-meter dimensions and binder material coating each of the metal particulates; and sintering the sinterable paste to create a sintered heat spreader in the substrate. 2. The method of claim 1 further comprising applying contact surfaces over top and bottom surfaces of the sintered heat spreader. 3. The method of claim 1 further comprising: applying a die-attach material over the sintered heat spreader; and attaching a semiconductor die to the die-attach material. 4. The method of claim 1 wherein the at least one cavity includes a first cavity in which the sintered heat spreader is formed and a second cavity in which a sintered via is formed by sintering the sinterable paste during the sintering step. 5. The method of claim 4 wherein the sintered heat spreader is larger than the sintered via. 6. The method of claim 4 further comprising applying contact surfaces over top and bottom surfaces of the sintered heat spreader and applying contact surfaces over top and bottom surfaces of the sintered via. 7. The method of claim 4 further comprising: applying a die-attach material over the sintered heat spreader; attaching a semiconductor die to the die-attach material; and connecting a pad on the semiconductor die to the sintered via using bond wire. 8. The method of claim 1 wherein the substrate is formed by laminate materials and comprises at least two electrical routing layers, wherein the laminate materials are resin coated glass weaved fiber. 9. The method of claim 1 wherein a thickness of the substrate is between 0.03 mm and 1.0 mm. 10. The method of claim 1 wherein the at least one cavity has a shape selected from a group consisting of a square shape, a rectangular shape, an “L” shape, a “T” shape, a circle shape, an oval shape, a cross shape, and a sawtooth shape. 11. The method of claim 1 wherein the metal particulates are selected from a group consisting of copper, silver and gold. 12. The method of claim 1 wherein the sinterable paste is sintered between 150° C. and 350° C. for a duration of 10 to 180 minutes. 13. The method of claim 1 wherein the size of the at least one cavity is between 0.25 mm×0.25 mm and 10 mm×10 mm. 14. The method of claim 3 wherein a thickness of the semiconductor die is between 0.05 mm and 0.5 mm. 15. The method of claim 3 wherein the die-attach material comprises sinterable material. 16. The method of claim 3 wherein the die-attach material comprises an epoxy material. 17. The method of claim 3 wherein a thickness of the die-attach material is between 0.025 mm and 0.150 mm. 18. An apparatus comprising: a substrate having at least one cavity that extends through the substrate from a top surface of the substrate to a bottom surface of the substrate, wherein the bottom surface of the substrate is opposite the top surface of the substrate; and a sintered heat spreader formed in the at least one cavity, wherein the sintered heat spreader is formed from a sinterable paste, which comprises metal particulates with sub-nano-meter dimensions and binder material coating each of the metal particulates. 19. The apparatus of claim 18 wherein the at least one cavity includes a first cavity in which the sintered heat spreader is formed and a second cavity in which a sintered via is formed. 20. The apparatus of claim 18 further comprising: a die-attach material over the sintered heat spreader; and a semiconductor die attached to the die-attach material.

Assignees

Inventors

Classifications

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • using a polymer adhesive, e.g. an adhesive based on silicone or epoxy · CPC title

  • Soldering or alloying · CPC title

  • Connecting techniques · CPC title

  • comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

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Frequently asked questions

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What does patent US9589864B2 cover?
The present disclosure relates to a substrate with an embedded sintered heat spreader and a process for making the same. According to an exemplary process, at least one cavity is created through the substrate. Sinterable paste including metal particulates and binder material is then dispensed into the at least one cavity. Next, the sinterable paste is sintered to create a sintered heat spreader…
Who is the assignee on this patent?
Rf Micro Devices Inc, Qorvo Us Inc
What technology area does this patent fall under?
Primary CPC classification H10W40/258. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 07 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).