Stacked semiconductor package

Patent metadata

Field	Value
Publication number	US-2016012864-A1
Application number	US-201414516012-A
Country	US
Kind code	A1
Filing date	Oct 16, 2014
Priority date	Jul 9, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

A stacked semiconductor package includes a package substrate, an interposer mounted on the package substrate, a plurality of semiconductor chips stacked on the interposer, and a control unit provided in the interposer, that stores in advance data to be written in the plurality of semiconductor chips, and that outputs the data stored in advance according a test mode signal.

First claim

What is claimed is:

1 . A stacked semiconductor package comprising:
a package substrate; an interposer mounted on the package substrate; a plurality of semiconductor chips stacked on the interposer; and a control unit provided in the interposer, that stores in advance data to be written in the plurality of semiconductor chips, and outputs the data stored in advance according to a test mode signal.

2 . The stacked semiconductor package according to claim 1 , wherein the control unit is configured to output the data stored in advance when the test mode signal is enabled, and to output data input from the package substrate or the plurality of semiconductor chips when the test mode signal is not enabled.

3 . The stacked semiconductor package according to claim 1 , wherein, when the test mode signal is enabled, the control unit is configured to selectively output the data stored in advance according to a minimum time tRTW for which write data is applied after a read operation.

4 . The stacked semiconductor package according to claim 3 , wherein the control unit outputs the data stored in advance when the minimum time tRTW, for which write data is applied after a read operation, is shorter than a preset time.

5 . The stacked semiconductor package according to claim 3 , wherein the control unit outputs data input from the plurality of semiconductor chips or the package substrate, when the minimum time tRTW, for which write data is applied after a read operation, is equal to or more than a preset time.

6 . A stacked semiconductor package comprising:
a package substrate; an interposer mounted on the package substrate; and a plurality of semiconductor chips stacked on the interposer, wherein the interposer comprises: is a latch section that stores in advance data to be written; and a selection section that is electrically coupled to the latch section and that selects and outputs the data stored in the latch section when a test mode signal is input.

7 . The stacked semiconductor package according to claim 6 , wherein the data stored in advance in the latch section is stored before the test mode signal is input.

8 . The stacked semiconductor package according to claim 7 , wherein, when the test mode signal is not input, the selection section selects and outputs data input from the package substrate or the plurality of semiconductor chips.

9 . The stacked semiconductor package according to claim 7 , wherein the selection section outputs the data stored in the latch section when a minimum time tRTW, for which write data is applied after a read operation, is shorter than a preset time.

10 . The stacked semiconductor package according to claim 9 , wherein the selection section outputs data input from the package substrate or the plurality of semiconductor chips when the minimum time tRTW, for which write data is applied after a read operation, is equal to or more than the preset time.

11 . The stacked semiconductor package according to claim 10 , wherein the interposer further comprises:
a signal generation section that generates a signal, wherein the signal generation section determines whether the minimum time tRTW, for which write data is applied after a read operation, is shorter than the preset time when the test mode signal is input, and generates a signal to allow the selection section to select output of the data stored in the latch section or to select output of the data input from the package substrate or the plurality of semiconductor chips according to a result of the determination.

12 . A stacked semiconductor package comprising:
a package substrate: a plurality of semiconductor chips stacked on an interposer, wherein the interposer is configured to receive a data enable signal and a data signal and store in advance data to be written, receive the output signal of the data signal, and output the output signal of the data signal based on a selection signal.

13 . The stacked semiconductor package according to claim 12 , wherein the interposer is configured to control a delay of a minimum time where data is applied after a read operation.

14 . The stacked semiconductor package according to claim 13 , wherein the interposer is configured to select and output data stored in advance according to the minimum time when a test mode signal is applied.

15 . The stacked semiconductor package according to claim 14 , wherein the data enable signal includes test mode information.

16 . The stacked semiconductor package according to claim 12 , further comprising:
a selection section configured to selectively output the output signal of a latch section or the data signal in response to the selection signal.

17 . The stacked semiconductor package according to claim 13 , further comprising:
a signal generation section configured to generate the selection signal by comparing a preset time to the minimum time.

18 . The stacked semiconductor package according to claim 17 , wherein when the minimum time is less than the preset time, the selection section outputs a latched data signal, and when the minimum time is greater than the preset time, the selection section outputs the data signal.

19 . The stacked semiconductor package according to claim 16 , wherein the interposer stores data received from the package is substrate in the latch section.

20 . The stacked semiconductor package according to claim 17 , wherein the signal generation section receives a test mode signal to compare the minimum time with the preset time.

Assignees

• Sk Hynix Inc

Inventors

• Park Min Su
• Ku Young Jun

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• G11C29/04

  Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals} · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title