Method and system for reproducing prototyping failures in emulation

Patent metadata

Field	Value
Publication number	US-9589084-B2
Application number	US-201414448708-A
Country	US
Kind code	B2
Filing date	Jul 31, 2014
Priority date	Jul 31, 2013
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

A method for simulating a circuit includes running a first prototype of the circuit a predetermined number of cycles behind a second prototype of the circuit, and running a hardware emulator of the circuit in accordance with an input trace received by the first prototype and the second prototype.

First claim

What is claimed is:

1. A method for verifying a circuit design, the method comprising:
providing first and second prototypes of the circuit;
applying a plurality of input signals to the second prototype of the circuit at a first point in time;
configuring the second prototype of the circuit to detect a condition;
applying the plurality of input signals to the first prototype of the circuit at a second point in time occurring after the first point in time by a predetermined number of cycles of a clock;
capturing a design state of the first prototype when the condition is met;
capturing at least a first subset of the plurality of input signals during a period defined by the first and second points in time;
configuring a hardware emulator to represent the circuit design;
loading the captured design state to the hardware emulator; and
applying the captured at least first subset of the plurality of input signals to the hardware emulator to verify the circuit design.

2. The method of claim 1 further comprising compiling a representation of the circuit design to form the first prototype and the second prototype.

3. The method of claim 2 , wherein compiling includes programming a plurality of logic blocks in one or more field programmable gate array (FPGA) chip.

4. The method of claim 2 , wherein compiling further includes compiling a register transfer logic (RTL) inference representing the circuit design into a plurality of design objects thereby forming a location database associated with the plurality of design objects, the design objects being implemented respectively in the first prototype, the second prototype, and the hardware emulator.

5. The method of claim 4 , wherein the location database maps the location of each of the plurality of design objects respectively in the first prototype, the second prototype, and the hardware emulator.

6. The method of claim 1 further comprising:
capturing a value stored in each of a plurality of registers disposed in the first prototype; and
loading each captured value in a different one of a plurality of registers disposed in the hardware emulator.

7. The method of claim 1 further comprising:
freezing a state of the first prototype when the condition in the second prototype is met.

8. The method of claim 1 further comprising:
freezing a state of the second prototype when the condition in the second prototype is met.

9. The method of claim 1 , wherein the first prototype and the second prototype are substantially identical to one another.

Assignees

• Synopsys Inc

Inventors

• Krupnova Helena
• Goel Yogesh

Classifications

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F2111/04

  Constraint-based CAD · CPC title

• G06F2115/06

  Structured ASICs · CPC title

• G06F30/331 Primary

  with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title