Fault-tolerance through silicon via interface and controlling method thereof

Patent metadata

Field	Value
Publication number	US-9588717-B2
Application number	US-201414578053-A
Country	US
Kind code	B2
Filing date	Dec 19, 2014
Priority date	Nov 12, 2014
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

A fault-tolerance through silicon via (TSV) interface is disposed in a three-dimensional random access memory (3-D RAM) with N memory layers and M data access path sets, and each of the memory layers containing K memory arrays, and each of the data access path sets containing a plurality of TSV paths connecting to the memory layers. The fault-tolerance TSV interface includes a path controlling unit and a processing unit. The path controlling unit detects and controls the data access path sets. When a fault occurs in any data access path set connecting to a memory layer, the processing unit provides at least two different fault-tolerance access configurations. In each of the fault-tolerance access configurations, μ data access path sets are enabled to access all K memory arrays in the corresponding memory layer, where 0<μ<M.

First claim

What is claimed is:

1. A fault-tolerance through silicon via interface, wherein the fault-tolerance through silicon via interface is disposed in a three-dimensional random access memory with N memory layers and M data access path sets, each of the memory layers contains K memory arrays, each of the data access path sets contains a plurality of through silicon via paths connecting to the N memory layers, and the fault-tolerance through silicon via interface comprises:
a path controlling unit, detecting and controlling the M data access path sets; and
a processing unit, wherein when a fault occurs in any of the data access path sets connecting to one of the N memory layers, two or more different fault-tolerance access configurations are provided; in each of the fault-tolerance access configurations, μ, data access path sets are enabled to access all K memory arrays on one of the N memory layers, where 0<μ<M; in the two or more different fault-tolerance access configurations, all of the K memory arrays in each of the N memory layers are accessed even if one of the through silicon via paths is failed.

2. The fault-tolerance through silicon via interface of claim 1 , further comprising:
a memory controlling unit, wherein in one of the fault-tolerance access configurations, the path controlling unit and the memory controlling unit select each of the μ data access path sets to access K/μ out of K memory arrays on the corresponding memory layer.

3. The fault-tolerance through silicon via interface of claim 1 , further comprising:
a memory controlling unit, wherein in one of the fault-tolerance access configurations, the path controlling unit and the memory controlling unit select each of the μ data access path sets to access two out of K memory arrays on the corresponding memory layer.

4. The fault-tolerance through silicon via interface of claim 1 , further comprising:
a memory controlling unit, wherein in one of the fault-tolerance access configurations, the path controlling unit and the memory controlling unit select each of the μ data access path sets to access all K memory arrays on the corresponding memory layer.

5. The fault-tolerance through silicon via interface of claim 1 , wherein in one of the fault-tolerance access configurations, the path controlling unit enables two out of M data access path sets connecting to the corresponding memory layer.

6. The fault-tolerance through silicon via interface of claim 1 , wherein in one of the fault-tolerance access configurations, the path controlling unit enables one out of M data access path set connecting to the corresponding memory layer.

7. The fault-tolerance through silicon via interface of claim 1 , further comprising:
a memory controlling unit, selecting the data access path sets to concurrently access 2 b out of N memory layers, where b is a natural number.

8. A controlling method of a fault-tolerance through silicon via interface, wherein the controlling method comprises:
providing a three-dimensional random access memory with N memory layers and M data access path sets, wherein each of the memory layers contains K memory arrays, each of the data access path sets contains a plurality of through silicon via paths connecting to the N memory layers, and the fault-tolerance through silicon via interface is disposed on each of the N memory layers; and
providing two or more different fault-tolerance access configurations, when a fault occurs in any of the data access path sets connecting to one of the N memory layers; wherein in each of the fault-tolerance access configurations, μ data access path sets are enabled to access all K memory arrays on one of the N memory layers, where 0<μ<M; in the two or more different fault-tolerance access configurations, all of the K memory arrays in each of the N memory layers are accessed even if one of the through silicon via paths is failed.

9. The controlling method of claim 8 , wherein one of the fault-tolerance access configurations has each of the μ data access path sets accessing K/μ memory arrays on the corresponding memory layer.

10. The controlling method of claim 8 , wherein one of the fault-tolerance access configurations has each of the μ data access path sets accessing two of the memory arrays on the corresponding memory layer.

11. The controlling method of claim 8 , wherein one or more of the fault-tolerance access configurations has each of the μ data access path sets accessing all K memory arrays on the corresponding memory layer.

12. The controlling method of claim 8 , wherein one or more of the fault-tolerance access configurations has two of the data access path sets connecting to the corresponding memory layer enabled.

13. The controlling method of claim 8 , wherein one or more of the fault-tolerance access configurations has one of the data access path sets connecting to the corresponding memory layer enabled.

14. The controlling method of claim 8 , wherein the data access path sets concurrently access 2 b out of N memory layers, where b is a natural number.

15. The controlling method of claim 8 , further comprising:
selecting six fault-tolerance access configurations using a 3-bit control signal.

16. A fault-tolerance through silicon via interface controlling method, comprising:
providing a three-dimensional random access memory with N memory layers and M data access path sets, wherein each of the memory layers contains K memory arrays, each of the data access path sets contains a plurality of through silicon via paths connecting to the N memory layers, and the fault-tolerance through silicon via interface is disposed on each of the N memory layers; and
providing two or more fault-tolerance access configurations, when a fault occurs in any of the data access path sets connecting to one of the N memory layers; wherein the access of the K memory layers is with different address sequence arrangements; in the two or more different fault-tolerance access configurations, all of the K memory arrays in each of the N memory layers are accessed even if one of the through silicon via paths is failed.

Assignees

• Ind Tech Res Inst

Inventors

• Lo Chih-Yen
• Kwai Ding-Ming
• Yang Chi-Chun
• Wu Kuan-Te
• Yu yun-chao
• Li Jin-Fu

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/247

  Dispositions of multiple bumps · CPC title

• H10W72/244

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• G06F3/0635

  by changing the path, e.g. traffic rerouting, path reconfiguration · CPC title