Flip flop circuit

Patent metadata

Field	Value
Publication number	US-9584099-B2
Application number	US-201414539407-A
Country	US
Kind code	B2
Filing date	Nov 12, 2014
Priority date	Aug 29, 2014
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

A flip-flop circuit includes a first latch, a second latch, and a trigger stage. The first latch is configured to set a first latch output signal based on a first latch input signal and a clock signal. The second latch is configured to set a second latch output signal based on a second latch input signal and the clock signal. The trigger stage is configured to generate the second latch input signal based on the first latch output signal. The trigger stage is configured to cause the second input signal to have different voltage swings based on the first latch output signal and the second latch output signal.

First claim

What is claimed is:

1. A flip-flop circuit, comprising:
a first latch configured to set a first latch output signal based on a first latch input signal and a clock signal;
a second latch configured to set a second latch output signal based on a second latch input signal and the clock signal; and
a trigger stage coupled with the first latch and the second latch, the trigger stage being configured to generate the second latch input signal based on at least the first latch output signal, the trigger stage being configured to cause the second latch input signal to have different voltage swings based on the first latch output signal and the second latch output signal, the trigger stage comprising:
a voltage setting circuit comprising an output node, the voltage setting circuit being
coupled to the second latch,
configured to receive the second latch output signal, and
configured to set a voltage at the output node to have different voltage levels based on different states of the second latch output signal.

2. The flip-flop circuit of claim 1 , wherein the trigger stage is further configured to cause the second latch input signal to have
a first voltage swing in response to a first state of the second latch output signal, and
a second voltage swing in response to a second state of the second latch output signal, the second voltage swing being less than the first voltage swing.

3. The flip-flop circuit of claim 2 , wherein the second voltage swing is greater than a threshold voltage of an N-type transistor of the first latch or greater than a threshold voltage of an N-type transistor of the second latch.

4. The flip-flop circuit of claim 1 , wherein the
voltage setting circuit is further configured to set the voltage at the output node of the voltage setting circuit to have
a first power supply voltage level in response to a first state of the second latch output signal,
and
a second power supply voltage level in response to a second state of the second latch output signal, the second power supply voltage level being less than the first power supply voltage level; and

the trigger stage further comprises a NAND gate comprising a first P-type transistor, a source of the first P-type transistor of the NAND gate being coupled with the output node of the voltage setting circuit.

5. The flip-flop circuit of claim 4 , wherein the NAND gate further comprises:
a second P-type transistor comprising:
a drain coupled with a drain of the first P-type transistor; and
a gate configured to receive the first latch output signal;

a first N-type transistor comprising a drain coupled with the drain of the first P-type transistor; and
a second N-type transistor comprising a drain coupled with a source of the first N-type transistor,
wherein
a gate of the first P-type transistor is configured to receive the clock signal;
a gate of the first N-type transistor is configured to receive one of the clock signal and the first latch output signal; and
a gate of the second N-type transistor is configured to receive the other one of the clock signal and the first latch output signal.

6. The flip-flop circuit of claim 1 , wherein the voltage setting circuit further comprises:
a power node configured to carry a first supply voltage having a first power supply voltage level;
a P-type transistor having a source coupled with the power node, a gate configured to receive the second latch output signal, and a drain coupled with the output node of the voltage setting circuit; and
a diode having an anode coupled with the power node and a cathode coupled with the output node of the voltage setting circuit.

7. The flip-flop circuit of claim 1 , wherein the voltage setting circuit further comprises:
a first power node configured to carry a first supply voltage having a first power supply voltage level;
a second power node configured to carry a second supply voltage having a second power supply voltage level;
a first switching device configured to electrically couple the first power node to the output node of the voltage setting circuit in response to a first state of the second latch output signal and to electrically decouple the first power node from the output node of the voltage setting circuit in response to a second state of the second latch output signal; and
a second switching device configured to electrically couple the second power node to the output node of the voltage setting circuit in response to the second state of the second latch output signal and to electrically decouple the second power node from the output node of the voltage setting circuit in response to the first state of the second latch output signal.

8. The flip-flop circuit of claim 1 , wherein the voltage setting circuit further comprises:
a power node configured to carry a first supply voltage having a first power supply voltage level;
a P-type transistor having a source coupled with the power node, a gate configured to receive the second latch output signal, and a drain coupled with the output node of the voltage setting circuit; and
an N-type transistor having a drain coupled with the power node, a gate configured to receive the second latch output signal, and a source coupled with the output node of the voltage setting circuit.

9. The flip-flop circuit of claim 1 , further comprising an input stage coupled with the first latch, the input stage being configured to output the first latch input signal based on one of a plurality of input signals.

10. The flip-flop circuit of claim 1 , wherein
the first latch is configured to
update a logical state of the first latch output signal based on the first latch input signal in response to a first state of the clock signal; and
hold the logical state of the first latch output signal in response to a second state of the clock signal, the first state and the second state of the clock signal being logically complementary to each other; and

the second latch is configured to
update a logical state of the second latch output signal based on the second latch input signal in response to the second state of the clock signal; and
hold the logical state of the second latch output signal in response to the first state of the clock signal.

11. The flip-flop circuit of claim 1 , wherein
the first latch comprises an AND-OR-INV compound logic gate comprising a first input node coupled to the trigger stage, the AND-OR-INV compound logic gate being configured to receive the second latch input signal; and
the second latch comprises an OR-AND-INV compound logic gate comprising a second input node coupled to the trigger stage, the OR-AND-INV compound logic gate being configured to receive the second latch input signal.

12. A flip-flop circuit, comprising:
a first latch configured to, based on a first signal and in response to a clock signal, generate a second signal;
a trigger stage coupled with the first latch and configured to generate a third signal based on the clock signal, the second signal, and a fourth signal; and
a second latch coupled with the trigger stage and configured to, based on the third signal and in response to the clock signal, generate the fourth signal,
the trigger stage comprising:
a voltage setting circuit comprising an output node and configured to set a voltage at the output node of the voltage setting circuit in response to the fourth signal; and
a logic gate circuit having a power node electrically coupled with the output node of the voltage setting circuit.

13. The flip-flop circuit of claim 12 , wherein the voltage setting circuit further comprises:
a power supply node configured to carry a first sup

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Chi-Lin
• Hsieh Shang-Chih
• Lu Lee-Chung
• Wu Chang-Yu

Classifications

• H03K3/3565

  Bistables with hysteresis, e.g. Schmitt trigger · CPC title

• G01R31/318541 Primary

  Scan latches or cell details · CPC title

• H03K3/356104 Primary

  using complementary field-effect transistors (H03K3/35625 takes precedence) · CPC title

• H03K3/356121

  with synchronous operation (H03K3/35613, H03K3/356147 take precedence) · CPC title

• H03K3/356017 Primary

  using additional transistors in the input circuit (H03K3/356104, H03K3/3562 take precedence) · CPC title