Flip-flop circuit

Patent metadata

Field	Value
Publication number	US-9356583-B2
Application number	US-201414472937-A
Country	US
Kind code	B2
Filing date	Aug 29, 2014
Priority date	Aug 29, 2014
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A flip-flop circuit includes a first latch, a trigger stage and a second latch. The first latch is configured to latch a selected signal in response to a first state of a clock signal, and provide a first output signal. The trigger stage receives the clock signal and the first output signal to provide a trigger signal. The trigger signal does not toggle as the clock signal transits. The second latch is configured to latch the trigger signal in response to a second state of the clock signal, and provide a second output signal. The first state and the second state of the clock signal are complementary to each other.

First claim

What is claimed is:

1. A flip-flop circuit, comprising:
a first latch configured to latch a selected signal in response to a first state of a clock signal and provide a first output signal;
a trigger stage, connected to the first latch, configured to provide a trigger signal based on the clock signal and the first output signal; and
a second latch, connected to the trigger stage, configured to latch the trigger signal in response to a second state of the clock signal and provide a second output signal, the first state and the second state of the clock signal being complementary to each other.

2. The circuit of claim 1 , wherein the trigger stage is configured to receive a controlled signal to clear the second output signal.

3. The circuit of claim 1 , wherein the trigger stage is configured to receive a controlled signal to inhibit the trigger signal from toggling.

4. The circuit of claim 1 , wherein the first latch is configured to hold the previously latched selected signal in response to the second state of the clock signal, and the second latch is configured to hold the previously latched trigger signal in response to the first state of the clock signal.

5. The circuit of claim 1 further comprising:
an input stage, connected to the first latch, configured to select one of input signals as the selected signal.

6. The circuit of claim 5 , wherein the input stage, first latch, trigger stage and second stage are formed in an AOI structure composed of logic AND gates, OR gates and inverters.

7. The circuit of claim 5 , wherein the input stage includes:
a first AND gate to receive a scan input signal;
a second AND gate to receive a data input signal; and
an OR gate to provide one of the scan input signal and the data input signal as the selected signal.

8. The circuit of claim 1 , wherein the first latch includes:
a first AND gate to receive the selected signal and the trigger signal;
a second AND gate to receive the clock signal; and
a NOR gate to receive an output each from the first AND gate and the second AND gate, and provide the first output signal.

9. The circuit of claim 1 , wherein the trigger stage includes:
a NAND gate to receive the clock signal and the first output signal, and provide the trigger signal.

10. The circuit of claim 1 , wherein the trigger stage includes:
a NOR gate to receive a controlled signal for clearing the second output signal.

11. The circuit of claim 1 , wherein the trigger stage includes:
a NAND gate to receive one of a scan input signal and a data input signal; and
a NOR gate to receive an output from the NAND gate for inhibiting the trigger signal from toggling.

12. The circuit of claim 1 , wherein the second includes:
an OR gate to receive the clock signal; and
a NAND gate to receive an output from the OR gate and the trigger signal.

13. A flip-flop circuit, comprising:
an input stage configured to select one of input signals for output;
a first latch configured to latch the selected signal in response to a first state of a clock signal in a clock cycle, and hold the previously latched selected signal in response to a second state of the clock signal in the clock cycle, the first state and the second state of the clock signal being complementary to each other;
a second latch configured to latch the selected signal in response to the second state of the clock signal in the clock cycle, and hold the previously latched selected signal latched in the previous clock cycle; and
a trigger stage connected between the first latch and the second latch, wherein the trigger stage is configured to provide a trigger signal based on the clock signal and an output signal from the first latch.

14. The circuit of claim 13 , wherein the trigger stage is configured to receive a controlled signal to clear an output signal at the second latch.

15. The circuit of claim 13 , wherein the trigger stage is configured to receive a controlled signal to inhibit the trigger signal from toggling.

16. A method of operating a flip-flop circuit, the method comprising:
selecting, at an input stage, one of input signals for output;
latching the selected input signal, at a first latch connected to the input stage, in response to a first state of a clock signal;
providing a trigger signal, at a trigger stage connected to the first latch, based on the clock signal and an output signal from the first latch; and
latching the trigger signal, at a second latch connected to the trigger stage, in response to a second state of the clock signal, the first state and the second state of the clock signal being complementary to each other.

17. The method of claim 16 further comprising:
providing a controlled signal to the trigger stage, the controlled signal causing the trigger signal to change to a predetermined state; and
clearing an output from the second latch, based on the trigger signal having the predetermined state.

18. The method of claim 16 further comprising:
providing a controlled signal in response to a predetermined state of the selected signal; and
inhibiting the trigger signal from toggling, based on the controlled signal.

19. The method of claim 16 further comprising:
holding the previously latched selected signal, at the first latch, in response to the second state of the clock signal; and
holding the previously latched trigger signal, at the second latch, in response to the first state of the clock signal.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Liu Chi-Lin
• Hsieh Shang-Chih
• Lu Lee-Chung
• Wu Chang-Yu

Classifications

• H03K3/3565

  Bistables with hysteresis, e.g. Schmitt trigger · CPC title

• H03K3/356121

  with synchronous operation (H03K3/35613, H03K3/356147 take precedence) · CPC title

• G01R31/318541 Primary

  Scan latches or cell details · CPC title

• H03K3/356017 Primary

  using additional transistors in the input circuit (H03K3/356104, H03K3/3562 take precedence) · CPC title

• H03K3/037 Primary

  Bistable circuits · CPC title