Tunable variable resistance memory device

Patent metadata

Field	Value
Publication number	US-9583703-B2
Application number	US-201514727618-A
Country	US
Kind code	B2
Filing date	Jun 1, 2015
Priority date	Jun 1, 2015
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

A variable resistance memory device may include a first electrode and a second electrode. The device may further include a chalcogenide glass layer between the first electrode and the second electrode. The chalcogenide glass layer may include a chalcogenide glass material co-deposited with a metal material. The device may also include a metal ion source structure between the chalcogenide glass layer and the second electrode. The device may include a buffer layer between the first electrode and the chalcogenide glass layer.

First claim

What is claimed is:

1. A variable resistance memory device comprising:
a first electrode and a second electrode;
a chalcogenide glass layer between the first electrode and the second electrode, the chalcogenide glass layer including a chalcogenide glass material co-deposited with a metal material;
a metal ion source structure between the chalcogenide glass layer and the second electrode; and
a buffer layer between the first electrode and the chalcogenide glass layer, wherein the buffer layer includes the chalcogenide glass material and excludes the metal material.

2. The device of claim 1 , wherein the metal material includes chromium, tungsten, copper, cobalt, indium, or a combination thereof.

3. The device of claim 1 , wherein the chalcogenide glass material includes germanium selenide.

4. The device of claim 1 , wherein the metal ion source structure includes:
a first adhesion layer and a second adhesion layer; and
a mobile metal layer between the first adhesion layer and the second adhesion layer.

5. The device of claim 4 , wherein the first adhesion layer and the second adhesion layer include the chalcogenide glass material.

6. The device of claim 4 , wherein the metal layer includes silver.

7. The device of claim 4 , wherein a thickness of the metal layer is between 600 Å and 1000 Å.

8. The device of claim 4 , wherein a thickness of the first adhesion layer and the second adhesion layer is less than 200 Å.

9. The device of claim 1 , further comprising a metal-chalcogenide layer between the chalcogenide glass layer and the metal ion source structure.

10. The device of claim 9 , wherein the metal chalcogenide layer includes tin-selenide.

11. The device of claim 9 , wherein a thickness of the metal chalcogenide layer is between 750 Å and 1250 Å.

12. The device of claim 1 , wherein a thickness of the chalcogenide glass layer is between 250 Å and 350 Å.

13. The device of claim 1 , wherein a thickness of the buffer layer is between 50 Å and 150 Å.

14. The device of claim 1 , further comprising another buffer layer between the chalcogenide glass layer and the metal ion source structure.

15. The device of claim 1 , wherein an electrical resistance between the first electrode and the second electrode is programmable within the range of 10 kΩ and 1 MΩ.

16. The device of claim 1 , wherein an electrical resistance between the first electrode and the second electrode is programmable within the range of 10 kΩ and 100 kΩ.

17. A variable resistance memory device comprising:
a first electrode and a second electrode;
a chalcogenide glass layer between the first electrode and the second electrode, the chalcogenide glass layer including germanium-telluride co-deposited with carbon;
a metal-chalcogenide layer between the chalcogenide glass layer and the second electrode; and
an ion source structure between the metal-chalcogenide layer and the second electrode.

18. The device of claim 17 , wherein the metal chalcogenide layer comprises a metal-selenide layer, the metal-selenide layer including tin-selenide.

19. The device of claim 17 , wherein the germanium-telluride is co-deposited with carbon using a co-sputtering process.

20. A method of forming a variable resistance memory device, the method comprising:
forming a first electrode;
forming a buffer layer;
forming a chalcogenide glass layer by co-depositing a chalcogenide glass material and a metal material, wherein the buffer layer includes the chalcogenide glass material and excludes the metal material;
forming an ion source structure; and
forming a second electrode.

21. The method of claim 20 , wherein the metal material includes a metal selected from the group consisting of chromium, tungsten, and copper, cobalt, indium, and combinations thereof.

22. The method of claim 20 , further comprising forming a metal chalcogenide layer between the chalcogenide glass layer and the ion source structure.

23. The method of claim 20 , wherein forming the ion source structure comprises:
forming a first adhesion layer;
forming a metal layer; and
forming a second adhesion layer.

24. A variable resistance memory device comprising:
a first electrode and a second electrode;
a chalcogenide glass layer between the first electrode and the second electrode, the chalcogenide glass layer including a chalcogenide glass material co-deposited with a metal material;
a metal ion source structure between the chalcogenide glass layer and the second electrode; and
a buffer layer between the first electrode and the chalcogenide glass layer, wherein the buffer layer continuously covers the first electrode.

25. The device of claim 24 , wherein the buffer layer includes the chalcogenide glass material and excludes the metal material.

Assignees

• Univ Boise State

Inventors

• Campbell Kristy A

Classifications

• H01L45/141 Primary

  Electricity · mapped topic

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• H01L45/1253

  Electricity · mapped topic

• H01L45/16

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic