Drain extended CMOS with counter-doped drain extension

Patent metadata

Field	Value
Publication number	US-9583596-B2
Application number	US-201514949241-A
Country	US
Kind code	B2
Filing date	Nov 23, 2015
Priority date	Nov 3, 2010
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.

First claim

What is claimed is:

1. A method of fabricating an integrated circuit, comprising the step of:
forming a drift region between a gate and a drain of a DEMOS transistor;
wherein at least 10 percent of a length of said drift region between said gate and said drain consists of a concentration of a first dopant type plus a concentration of scattering centers; and
wherein said concentration of said scattering centers is greater than said concentration of said first dopant type divided by 5.

2. The method of claim 1 , wherein said concentration of said scattering centers is a dopant of a second dopant type.

3. The method of claim 2 , wherein said concentration of said first dopant type is an n-type dopant in the range of 1E15/cm 3 to 1E18/cm 3 and wherein said second dopant type is a p-type dopant with a concentration between 0.2 and 0.9 of said first dopant type concentration.

4. The method of claim 3 , wherein said concentration of said n-type dopant is about 5E16/cm 3 and wherein said concentration of said second dopant type is about 3E16/cm 3 .

5. The method of claim 1 , wherein said concentration of said scattering centers is silicon, germanium, or carbon.

6. The method of claim 5 , wherein said concentration of said first dopant is between 1E15/cm 3 to 1E18/cm 3 and wherein said concentration of said scattering centers is between 1E15/cm 3 to 1E18/cm 3 .

7. The method of claim 6 , wherein said concentration of said first dopant is about 2E16/cm 3 and wherein said concentration of said scattering centers is about 6E16/cm 3 .

8. The method of claim 1 , wherein a first portion of said concentration of said scattering centers are a second dopant type, wherein a concentration of said second dopant type is between 0.2 and 0.9 times the said concentration, and wherein a second portion of said scattering centers are at least one of silicon, germanium, and carbon.

9. A method of fabricating an integrated circuit, comprising the step of:
forming a gate of a DEMOS transistor over a substrate;
forming a source and drain of the DEMOS transistor in the substrate;
forming a drift region the DEMOS transistor between the gate and drain by:
implanting a first dopant type into a region of the substrate; and
adding a concentration of scattering centers by counterdoping the region with a second dopant type, wherein at least 10 percent of a length of said drift region between said gate and said drain consists of a concentration of a first dopant type plus a concentration of scattering centers; and

wherein said concentration of said scattering centers is greater than said concentration of said first dopant type divided by 5.

10. The method of claim 9 , wherein said concentration of said first dopant type is an n-type dopant in the range of 1E15/cm 3 to 1E18/cm 3 and wherein said second dopant type is a p-type dopant with a concentration between 0.2 and 0.9 of said first dopant type concentration.

11. The method of claim 9 , wherein said concentration of said n-type dopant is about 5E16/cm 3 and wherein said concentration of said second dopant type is about 3E16/cm 3 .

Assignees

• Texas Instruments Inc

Inventors

• Steinmann Philipp
• Chatterjee Amitava
• Pendharkar Sameer

Classifications

• H10D8/20

  Breakdown diodes, e.g. avalanche diodes · CPC title

• H10D30/603

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F17/5081

  Physics · mapped topic

• H01L29/7835

  Electricity · mapped topic