Integrated circuit devices including FinFETs and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9583590-B2
Application number	US-201514698402-A
Country	US
Kind code	B2
Filing date	Apr 28, 2015
Priority date	Sep 27, 2013
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

Methods of forming a finFET are provided. The methods may include forming a fin-shaped channel region including indium (In) on a substrate, forming a deep source/drain region adjacent to the channel region on the substrate and forming a source/drain extension region between the channel region and the deep source/drain region. Opposing sidewalls of the source/drain extension region may contact the channel region and the deep source/drain region, respectively, and the source/drain extension region may include In y Ga 1−y As, and y is in a range of about 0.3 to about 0.5.

First claim

What is claimed:

1. A method of forming a finFET, the method comprising:
forming a channel region comprising indium (In) on a substrate, the channel region having a fin shape;
forming a source/drain extension region adjacent to the channel region, the source/drain extension region comprising a first sidewall that contacts the channel region and a second sidewall opposite the first sidewall; and
forming a deep source/drain region contacting the second sidewall of the source/drain extension region,
wherein the source/drain extension region is between the channel region and the deep source/drain region,
wherein the source/drain extension region comprises In y Ga 1−y As, and y is in a range of about 0.3 to about 0.5 and
wherein the deep source/drain region comprises In z Ga 1−z As.

2. The method of claim 1 , wherein an indium concentration in the channel region is greater than an indium concentration in the source/drain extension region.

3. The method of claim 2 , wherein forming the channel region comprises forming the channel region comprising In x Ga 1−x As, and x is in a range of about 0.5to about 0.6.

4. The method of claim 3 , wherein x is about 0.53.

5. The method of claim 4 , wherein y is about 0.4.

6. The method of claim 3 , wherein an indium concentration in the deep source/drain region is greater than the indium concentration in the channel region.

7. The method of claim 6 , wherein z is in a range of about 0.6to about 1.

8. The method of claim 6 , further comprising forming a contact region contacting an upper surface of the deep source/drain region, wherein a portion of the deep source/drain region contacts the contact region and comprises pure InAs.

9. The method of claim 3 , wherein the substrate comprises an InP substrate or In a Ga 1−a As, and a is about 0.53or less.

10. The method of claim 3 , wherein:
the substrate comprises an InP substrate; and
forming the channel region comprising In x Ga 1−x As comprises forming an In x Ga 1−x As pattern that is lattice matched to the InP substrate.

11. The method of claim 1 , wherein forming the channel region and the source/drain extension region comprises:
forming a preliminary channel region on the substrate;
forming a mask pattern on the preliminary channel region;
etching the preliminary channel region using the mask pattern as an etching mask to form the channel region; and
epitaxially growing the source/drain extension region using the channel region as a seed layer.

12. The method of claim 1 , wherein:
forming the deep source/drain region comprises forming a first deep source/drain region that is adjacent to a first sidewall of the channel region such that the first sidewall of the source/drain extension region contacts the first sidewall of the channel region; and
the method further comprises forming a second deep second source/drain region contacting a second sidewall of the channel region opposite the first sidewall of the channel region.

13. The method of claim 1 , wherein a width of the source/drain extension region in a direction from the channel region to the deep source/drain region is about 10 nm.

14. The method of claim 1 , further comprising forming a gate electrode overlying the channel region, wherein the first sidewall of the source/drain extension region is substantially aligned to a sidewall of the gate electrode such that a junction is formed in the source/drain extension region.

15. The method of claim 1 , wherein z is greater than y.

16. The method of claim 15 , wherein forming the channel region comprises forming the channel region comprising In x Ga 1−x As, and x is greater than y.

17. A method of forming a finFET, the method comprising:
forming a channel region comprising a first semiconductor material on a substrate, the channel region having a fin shape;
forming a barrier layer on a sidewall of the channel region, the barrier layer comprising the first semiconductor material and a second semiconductor material; and
forming a source/drain region on a sidewall of the barrier layer, the source/drain region comprising the first semiconductor material,
wherein a first concentration of the first semiconductor material in the barrier layer is less than a second concentration of the first semiconductor material in the channel region and is less than a third concentration of the first semiconductor material in the source/drain region.

18. The method of claim 17 , wherein:
the first semiconductor material comprises Indium (In), and the second semiconductor material comprises gallium (Ga); and
wherein the third concentration of the first semiconductor material in the source/drain region is greater than the second concentration of the first semiconductor material in the channel region.

19. The method of claim 18 , wherein forming the channel region comprises forming the channel region comprising In x Ga 1−x ,As, and x is in a range of about 0.5to about 0.6.

20. The method of claim 17 , wherein forming the channel region and the barrier layer comprises:
forming a preliminary channel region on the substrate;
forming a mask pattern on the preliminary channel region;
etching the preliminary channel region using the mask pattern as an etching mask to form the channel region; and
epitaxially growing the barrier layer using the channel region as a seed layer.

21. The method of claim 17 , wherein:
forming the source/drain region comprises forming a first source/drain region on a first sidewall of the channel region such that the barrier layer is disposed between the first sidewall of the channel region and a sidewall of the first source/drain region; and
the method further comprises forming a second source/drain region contacting a second sidewall of the channel region opposite the first sidewall of the channel region.

22. The method of claim 17 , wherein a width of the barrier layer in a direction from the channel region to the source/drain region is about 10 nm.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Obradovic Borna J
• Bowen Robert C
• Rodder Mark S

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H01L21/3086

  Electricity · mapped topic

• H01L21/823431

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic