Poly sandwich for deep trench fill

Patent metadata

Field	Value
Publication number	US-9583579-B2
Application number	US-201615191656-A
Country	US
Kind code	B2
Filing date	Jun 24, 2016
Priority date	Nov 26, 2014
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate comprising a semiconductor material;
a deep trench structure in the substrate, comprising:
a deep trench at least 10 microns deep in the substrate;
a dielectric liner disposed on sidewalls of the deep trench;
a first layer of polysilicon disposed on the dielectric liner and extending to a bottom of the deep trench; and
a second layer of polysilicon disposed on the first layer of polysilicon and extending into the deep trench, wherein dopants are distributed throughout the first layer of polysilicon and the second layer of polysilicon with an average doping density of at least 1×10 18 cm −3 , and wherein a width of the deep trench structure is 1.5 microns to 3.5 microns.

2. The semiconductor device of claim 1 , wherein the dielectric liner includes a layer of thermal oxide on the sidewalls and a layer of deposited silicon dioxide on the layer of thermal oxide.

3. The semiconductor device of claim 1 , wherein the deep trench structure is 20 microns to 35 microns deep in the substrate.

4. The semiconductor device of claim 1 , wherein the first layer of polysilicon has a thickness of 150 nanometers to 200 nanometers.

5. The semiconductor device of claim 1 , wherein a bottom of the deep trench structure is free of the dielectric liner so that the first layer of polysilicon makes an electrical contact to the semiconductor material of the substrate.

6. The semiconductor device of claim 5 , wherein the substrate includes a buried layer, and the deep trench extends below a bottom surface of the buried layer.

7. The semiconductor device of claim 1 , wherein the first layer of polysilicon is isolated from the substrate by the dielectric liner at a bottom of the deep trench structure.

Assignees

• Texas Instruments Inc

Inventors

• Hu Binghua
• Pendharkar Sameer P
• Jacobs Jarvis Benjamin

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/1406

  by ion implantation · CPC title

• H10P32/302

  Doping polycrystalline silicon or amorphous silicon layers · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title