Semiconductor device

Patent metadata

Field	Value
Publication number	US-9583455-B2
Application number	US-201615092864-A
Country	US
Kind code	B2
Filing date	Apr 7, 2016
Priority date	May 31, 2013
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

Reliability of a semiconductor device is improved. A semiconductor device has a base material of insulating material having a through hole, a terminal formed on a lower surface of the base material, and a semiconductor chip mounted on an upper surface of the base material in a face-up manner. The semiconductor device has a conductive member such as a wire, which electrically connects a pad of the semiconductor chip with an exposed surface of the terminal which is exposed from the through hole of the base material, and has a sealing body for sealing the conductive member, inside of the through hole of the base material, and the semiconductor chip. An anchor is provided in a region of the exposed surface of the terminal which is exposed from the through hole of the base material except for a joint portion joined with the conductive member.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate comprising:
a base material having a first surface, a second surface opposite to the first surface, and a through hole formed from one of the first surface and the second surface toward the other one, the base material being comprised of an insulating material; and
an external terminal formed on the second surface of the base material, the external terminal being comprised of a metal material;
a semiconductor chip having a principal surface, a pad formed on the principal surface, and a back surface opposite to the principal surface, and mounted on the first surface of the base material such that the back surface faces the first surface of the base material;
a plating layer formed inside of the through hole and also formed on an exposed surface of the external terminal, the exposed surface being exposed from the through hole of the base material when seen from the first surface of the base material;
a wire electrically connecting the pad of the semiconductor chip with the external terminal of the substrate, the wire having a first part connected to a surface of the plating layer, and a second part opposite to the first part;
a plurality of first stud bumps formed on the surface of the plating layer such that the first part of the wire is surrounded by the plurality of first stud bumps in plan view; and

a sealing body sealing inside of the through hole of the base material, the semiconductor chip, the wire and the plurality of first stud bumps,
wherein each of the plurality of first stud bumps has a first portion connected to the surface of the plating layer, and a second portion not connected to the surface of the plating layer, and
wherein the second portion of each of the plurality of first stud bumps is in contact with the sealing body.

2. The semiconductor device according to claim 1 , wherein a part of the sealing body is located between the second portion of each of the plurality of first stud bumps and the surface of the plating layer in cross-section view.

3. The semiconductor device according to claim 1 , wherein the second part of the wire is electrically connected with the pad of the semiconductor chip via a second stud bump.

4. The semiconductor device according to claim 1 ,
wherein a plurality of third stud bumps are stacked on the plurality of first stud bumps, respectively.

5. The semiconductor device according to claim 1 , wherein the wire and the plurality of first stud bumps are made of the same metal material as each other.

6. The semiconductor device according to claim 1 , wherein, in plan view, the first part of the wire is located at a position spaced apart from the central portion of the surface of the plating layer.

7. The semiconductor device according to claim 6 , wherein, in plan view, the first part of the wire is located away from the semiconductor chip than the central portion of the surface of the plating layer.

8. The semiconductor device according to claim 1 , wherein the first part of the wire is a ball portion having a diameter larger than a diameter of a third part of the wire between the first part and the second part.

Assignees

• Renesas Electronics Corp

Inventors

• Oyachi Kenji
• Wada Tamaki
• Morinaga Yuichi

Classifications

• H10W70/6525

  for securing the interconnections to the substrate, e.g. to prevent peeling · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title