Manufacturing method of semiconductor structure

Patent metadata

Field	Value
Publication number	US-9583394-B2
Application number	US-201615293292-A
Country	US
Kind code	B2
Filing date	Oct 14, 2016
Priority date	Jun 9, 2015
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

The present invention provides a method for forming a semiconductor structure, comprising: firstly, a substrate is provided, having a first fin structure and a second fin structure disposed thereon, next, a first isolation region is formed between the first fin structure and the second fin structure, a second isolation region is formed opposite the first fin structure from the first isolation region, and at least an epitaxial layer is formed on the side of the first fin structure and the second fin structure, wherein the epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region, in addition, the epitaxial layer has a stepped-shaped sidewall profile.

First claim

What is claimed is:

1. A method for forming a semiconductor structure, comprising:
providing a substrate having a first fin structure and a second fin structure disposed thereon;
forming a first isolation region located between the first fin structure and the second fin structure;
forming a second isolation region located opposite the first fin structure from the first isolation region; and
forming at least an epitaxial layer disposed on the side of the first fin structure and the second fin structure, wherein the epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region, in addition, the epitaxial layer has a stepped-shaped sidewall profile.

2. The method of claim 1 , wherein the step for forming the first fin structure and the second fin structure on the substrate comprising:
forming a plurality of third fins on the substrate;
forming a patterned hard mask on the substrate and covering parts of each third fin; and
performing an etching process to remove parts of each third fin, after the etching process is performed, the rest of the third fins being defined as the first fin structure and the second fin structure.

3. The method of claim 2 , further comprising forming at least one gate structure crossing over the first fin structure and the second fin structure.

4. The method of claim 3 , wherein the step for forming the first fin structure and the second fin structure is performed before the step for forming the gate structure.

5. The method of claim 3 , wherein the gate structure covers the first fin structure asymmetrically.

6. The method of claim 1 , wherein after the first fin structure and the second fin structure are formed on the substrate, the first isolation region and the second isolation region are then formed in the substrate.

7. The method of claim 1 , wherein the depth of the second isolation region is larger than the depth of the first isolation region.

8. The method of claim 1 , wherein the bottom surface of the epitaxial layer is a flat surface, and the epitaxial layer further comprises two sidewalls.

9. The method of claim 8 , wherein the angle between the flat surface and one of the sidewall is larger than 90 degrees.

10. The method of claim 1 , wherein the bottom surface of the epitaxial layer has an angle.

Assignees

• United Microelectronics Corp

Inventors

• Feng li-wei
• Tsai Shih-Hung
• Liu Hon-Huei
• Lin Chao-Hung
• Huang Nan-Yuan
• Jenq Jyh-Shyang

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L29/42372

  Electricity · mapped topic

• H01L21/308

  Electricity · mapped topic