Wafer processing method

US9583391B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9583391-B2
Application numberUS-201615202142-A
CountryUS
Kind codeB2
Filing dateJul 5, 2016
Priority dateJul 6, 2015
Publication dateFeb 28, 2017
Grant dateFeb 28, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

There is provided a wafer processing method including a modified layer forming step. In the wafer processing method, the power of a pulse laser beam set in the modified layer forming step is set to a power that forms modified layers and cracks in such a manner that a wafer is allowed to be divided into individual device chips before the thickness of the wafer reaches a finished thickness and, after the wafer is divided into the individual device chips, the time until the thickness of the wafer reaches the finished thickness is such a time that damage due to rubbing of the individual device chips against each other is not caused through grinding under a predetermined grinding condition set in a back surface grinding step.

First claim

Opening claim text (preview).

What is claimed is: 1. A wafer processing method for dividing a wafer on which a plurality of devices are formed on a front surface and are marked out by planned dividing lines into individual device chips, the wafer processing method comprising: a protective member disposing step of disposing a protective member on the front surface of the wafer; a modified layer forming step of positioning a light focus point of a pulse laser beam having such a wavelength as to be transmitted through the wafer on which the protective member is disposed at inside of the wafer along the planned dividing lines and irradiating the wafer with the pulse laser beam with predetermined power to form modified layers and cracks extending from the modified layers toward the front surface and a back surface; and a back surface grinding step of, after carrying out the modified layer forming step, holding a side of the protective member on a chuck table and grinding the back surface of the wafer by a grinding wheel under a predetermined grinding condition to divide the wafer into the individual device chips and carrying out grinding until the modified layers are removed and thickness of the wafer reaches a target finished thickness, wherein the predetermined power of the pulse laser beam set in the modified layer forming step is set to a power that forms the modified layers and the cracks in such a manner that the wafer is allowed to be divided into the individual device chips before the thickness of the wafer reaches the target finished thickness and, after the wafer is divided into the individual device chips, a time until the thickness of the wafer reaches the target finished thickness is such a time that damage due to rubbing of the individual device chips against each other is not caused through grinding under the predetermined grinding condition set in the back surface grinding step.

Assignees

Inventors

Classifications

  • H10P54/00Primary

    Cutting or separating of wafers, substrates or parts of devices · CPC title

  • H10P58/00Primary

    Singulating wafers or substrates into multiple chips, i.e. dicing · CPC title

  • for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks · CPC title

  • taking account of the properties of the material involved (B23K26/32, B23K26/40 take precedence) · CPC title

  • being semiconducting · CPC title

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What does patent US9583391B2 cover?
There is provided a wafer processing method including a modified layer forming step. In the wafer processing method, the power of a pulse laser beam set in the modified layer forming step is set to a power that forms modified layers and cracks in such a manner that a wafer is allowed to be divided into individual device chips before the thickness of the wafer reaches a finished thickness and, a…
Who is the assignee on this patent?
Disco Corp
What technology area does this patent fall under?
Primary CPC classification H10P54/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 28 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).