Gradient metal liner for interconnect structures
US-2024332075-A1 · Oct 3, 2024 · US
US9583389B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9583389-B2 |
| Application number | US-201514960104-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 4, 2015 |
| Priority date | Dec 18, 2013 |
| Publication date | Feb 28, 2017 |
| Grant date | Feb 28, 2017 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a metallization structure for an integrated circuit involves forming an exposed surface above a substrate, the exposed surface including regions of exposed dielectric material and regions of exposed metal. The method also involves forming, using a selective metal deposition process, a metal layer on the regions of exposed metal without forming the metal layer on the regions of exposed dielectric material.
Opening claim text (preview).
What is claimed is: 1. A method of fabricating a metallization structure for an integrated circuit, the method comprising: forming an exposed surface above a substrate, the exposed surface comprising regions of exposed dielectric material and regions of exposed metal; and forming, using a selective metal deposition process, a metal layer on the regions of exposed metal without forming the metal layer on the regions of exposed dielectric material, wherein forming the metal layer by using the selective metal deposition process comprises forming a molybdenum (Mo) metal layer. 2. The method of claim 1 , wherein forming the metal layer by using the selective metal deposition process comprises using a precursor molecule possessing electron-acceptor ligands on a late transition metal center. 3. The method of claim 2 , wherein using the precursor molecule comprises using an N,N′-dialkyl-diazabutadiene metal precursor complex. 4. The method of claim 3 , wherein the N,N′-dialkyl-diazabutadiene metal precursor complex includes Mo as the late transition metal center. 5. The method of claim 4 , wherein the N,N′-dialkyl-diazabutadiene metal precursor complex has three N,N′-dialkyl-diazabutadiene ligands. 6. The method of claim 1 , wherein forming the metal layer by using the selective metal deposition process comprises forming the metal layer at a temperature approximately in the range of 175-275 degrees Celsius. 7. The method of claim 1 , wherein the exposed dielectric material layer is selected from the group consisting of silicon dioxide and a low-k dielectric material. 8. A method of fabricating a metallization structure for an integrated circuit, the method comprising: forming a plurality of tungsten (W) contacts in a dielectric layer to provide exposed regions of the dielectric layer and exposed regions of the tungsten contacts; and forming, using a selective metal atomic layer deposition (ALD) or chemical vapor deposition (CVD) process, a metal layer on the exposed regions of the tungsten contacts without forming the metal layer on the exposed regions of the dielectric layer, wherein the metal layer is a molybdenum (Mo) metal layer. 9. The method of claim 8 , wherein forming the metal layer by using the selective metal ALD or CVD process comprises using an N,N′-dialkyl-diazabutadiene metal precursor complex. 10. The method of claim 9 , wherein the N,N′-dialkyl-diazabutadiene metal precursor complex includes Mo as a metal center, and wherein the N,N′-dialkyl-diazabutadiene metal precursor complex has three N,N′-dialkyl-diazabutadiene ligands. 11. The method of claim 9 , wherein forming the metal layer by using the selective metal ALD or CVD process comprises forming the metal layer at a temperature approximately in the range of 175-275 degrees Celsius.
by forming self-aligned vias · CPC title
from metallo-organic compounds · CPC title
Atomic layer deposition [ALD] · CPC title
Coating on selected surface areas, e.g. using masks · CPC title
using selective deposition · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.