Method for forming spacers for a transistor gate

Patent metadata

Field	Value
Publication number	US-9583339-B2
Application number	US-201615091916-A
Country	US
Kind code	B2
Filing date	Apr 6, 2016
Priority date	Dec 28, 2012
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

A method is provided for forming spacers for a gate of a field effect transistor, the gate being situated above a layer of semiconductor material, including forming a layer of nitride covering the gate; modifying the layer by plasma implantation of light ions, having an atomic number equal or less than 10, in the layer in order to form a modified layer of nitride, the modifying being performed so as not to modify the layer of nitride over its entire thickness at flanks of the gate; and removing the modified layer of nitride by a selective wet or dry etching, of the modified layer relative to said layer of semiconductor material and relative to the non-modified layer at the flanks of the gate, without etching the layer of semiconductor material, wherein an entire length of the non-modified layer at the flanks remains after the selective wet or dry etching.

First claim

The invention claimed is:

1. A method for forming spacers for a gate of a field effect transistor, the gate being situated above a layer of semiconductor material, comprising:
forming a layer of nitride covering the gate;
modifying the layer of nitride by plasma implantation of light ions, having an atomic number equal or less than 10, in the layer of nitride in order to form a modified layer of nitride, the modifying being performed so as not to modify the layer of nitride over its entire thickness at flanks of the gate; and
removing the modified layer of nitride by a selective wet etching, or a selective dry etching, of the modified layer of nitride relative to said layer of semiconductor material and relative to the non-modified layer of nitride at the flanks of the gate, without etching the layer of semiconductor material,
wherein an entire length of the non-modified layer of nitride at the flanks of the gate remains after the selective wet etching, or after the selective dry etching.

2. The method according to claim 1 , wherein the implantation of light ions and the implanted dose are implemented so that the modified layer of nitride is configured to be etched selectively relative to said layer of semiconductor material and relative to the non-modified layer of nitride.

3. The method according to claim 1 , wherein the layer of nitride is a layer of silicon nitride.

4. The method according to claim 1 , wherein the modifying the layer of nitride by plasma implantation modifies the layer of nitride continuously from a surface of the nitride layer to a depth in the nitride layer between 1 nm and 30 nm.

5. The method according to claim 1 , wherein the modifying the layer of nitride is preceded by anisotropic etching.

6. The method according to claim 5 , wherein the anisotropic etching comprises a dry etching in a plasma based on methyl fluoride (CH 3 F).

7. The method according to claim 1 , wherein the modifying comprises putting the layer of nitride in a presence of the plasma comprising the light ions in an etching reactor.

8. The method according to claim 1 , wherein the modifying includes implantation of light ions by an implanter.

9. The method according to claim 1 ,
wherein the layer of semiconductor material is at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and
wherein the selective wet etching, or the selective dry etching, is selective to the layer of semiconductor material and/or an oxide of the semiconductor material.

10. The method according to claim 9 , wherein the wet etching is selective to silicon by a solution based on hydrofluoric acid (HF).

11. The method according to claim 9 , wherein the wet etching is selective to silicon and includes applying a solution based on phosphoric acid (H 3 PO 4 ).

12. The method according to claim 1 , wherein the layer of semiconductor material includes silicon (Si), and wherein the dry etching is selective to the silicon (Si) and/or to silicon oxide (SiO 2 ).

13. The method according to claim 12 , wherein the dry etching is performed in a plasma formed in a confined chamber using nitrogen trifluoride (NF 3 ) and ammonia (NH 3 ).

14. The method according to claim 1 , wherein the dry etching comprises:
dry etching consisting of formation of solid salts; and
sublimating the solid salts.

15. The method according to claim 1 , wherein the modifying the layer of nitride and the removing the modified layer of nitride are performed within a single plasma reactor.

16. The method according to claim 1 , the modifying being a single step modification performed so as to modify the layer of nitride throughout its thickness over all surfaces parallel to a plane of a substrate on which the gate rests and so as not to modify the layer of nitride throughout its thickness on surfaces perpendicular to the plane.

17. The method according to claim 1 ,
wherein the modifying and removing include multiple sequences each comprising a step of modification and a step of removal, and
wherein, during at least one of the steps of modification, only part of the thickness of the layer of nitride is modified.

18. The method according to claim 17 , wherein the multiple sequences are repeated until the layer of nitride disappears on all surfaces parallel to a plane of a substrate on which the gate rests.

19. The method according to claim 1 , wherein the gate of the field effect transistor is situated on a stack of layers forming an elaborate substrate of silicon on insulator (SOI).

20. The method according to claim 1 , wherein the layer of semiconductor material is at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe).

21. The method according to claim 1 , wherein the selective wet etching is selective to silicon oxide (SiO 2 ).

22. The method according to claim 1 , wherein the light ions include at least one of helium (He) and hydrogen (H 2 ).

23. The method according to claim 1 , wherein the field effect transistor is a FDSOI transistor.

24. The method according to claim 1 , wherein the field effect transistor is a FinFET transistor.

25. The method according to claim 1 ,
wherein the plasma implantation of light ions comprises at least two plasma implantations having different implantation directions, and
wherein, to modify the direction of the plasma implantation, the layer of nitride is inclined.

26. A method of etching a layer of nitride selectively relative to silicon (Si) and/or silicon oxide (SiO 2 ), comprising:
at least one step of modifying all or part of the layer of nitride by plasma implantation of hydrogen (H 2 ) or helium (He) in the layer of nitride in order to form a modified layer of nitride, wherein the at least one step of modifying comprises putting the layer of nitride in a presence of a plasma comprising hydrogen ions or helium ions in an etching reactor; and
at least one step of removing the modified layer of nitride by selective wet etching, or selective dry etching, of the modified layer of nitride relative to the silicon (Si) and/or silicon oxide (SiO 2 ) from all surfaces parallel to a plane of a substrate on which a gate rests,
wherein the selective wet etching, or the selective dry etching, does not remove an entire length of the layer of nitride on surfaces perpendicular to the plane.

27. The method according to claim 26 , wherein the selective wet etching includes applying a solution based on phosphoric acid (H 3 PO 4 ).

28. The method according to claim 26 , wherein the selective wet etching includes applying a solution based on hydrofluoric acid (HF).

Assignees

• Commissariat Energie Atomique
• Cnrs Centre Nat De La Rech Scient
• Applied Materials Inc
• Cnrs-Centre Nat De La Rech Scient

Inventors

• Posseme Nicolas
• David Thibaut
• Joubert Olivier
• Lill Thorsten
• Nemani Srinivas
• Vallier Laurent

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title