Tungsten gates for non-planar transistors

Patent metadata

Field	Value
Publication number	US-9580776-B2
Application number	US-201514860341-A
Country	US
Kind code	B2
Filing date	Sep 21, 2015
Priority date	Sep 30, 2011
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.

First claim

What is claimed is:

1. A device, comprising:
a substrate, wherein the substrate comprises a silicon fin;
a first dielectric layer on the substrate, wherein the first dielectric layer comprises silicon and oxygen;
a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises hafnium and oxygen;
a pair of gate spacers on the substrate, wherein the gate spacers comprise a dielectric material;
an NMOS metal gate electrode above the second dielectric layer and between the pair of gate spacers, wherein the NMOS metal gate electrode comprises:
a first metal layer proximate the pair of gate spacers and above the second dielectric layer, wherein the first metal layer comprises titanium and nitrogen; and
a second metal layer on the first metal layer, wherein the second metal layer comprises tungsten;

a source region proximate to one of the pair of gate spacers, and a drain region proximate the other one of the pair of gate spacers, wherein the source region and the drain region comprise an n-type dopant;
a first contact coupled to the source region, wherein the first contact comprises a tungsten material above a first barrier layer; and
a second contact coupled to the drain region, wherein the second contact comprises a tungsten material above a second barrier layer.

2. The device of claim 1 , wherein the NMOS metal gate electrode is non-planar.

3. The device of claim 1 , wherein the NMOS work function material comprises between about 20 percent by weight to about 40 percent by weight aluminum, between about 30 weight percent to about 50 weight percent titanium, and between about 10 weight percent to about 30 weight percent carbon.

4. The device of claim 1 , further including a capping dielectric structure disposed adjacent the NMOS metal gate electrode and between the pair of gate spacers.

5. The device of claim 1 , wherein the second dielectric layer comprises a high k dielectric layer.

6. The device of claim 1 , wherein the first metal layer comprises a barrier layer.

7. The device of claim 1 , wherein the second metal layer comprises a fill layer.

8. The device of claim 1 , wherein a material composition of a dielectric material directly adjacent the pair of spacers differs from the material composition of the pair of gate spacers.

9. An assembly, comprising:
a first transistor comprising:
a substrate, wherein the substrate comprises a silicon fin;
a first dielectric layer on the substrate, wherein the first dielectric layer comprises silicon and oxygen;
a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises hafnium and oxygen;
a pair of gate spacers on the substrate, wherein the gate spacers comprise a dielectric material;
a NMOS metal gate electrode above the second dielectric material and between the pair of gate spacers, wherein the first NMOS metal gate electrode comprises:
a work function layer proximate the pair of gate spacers and above the second dielectric layer, wherein the work function layer comprises aluminum, titanium and carbon;
a barrier layer on the work function layer, wherein the barrier layer comprises titanium and nitrogen;

a source region proximate to one of the pair of gate spacers, and a drain region

proximate the other one of the pair of gate spacers, wherein the source region and the drain region comprise an n-type dopant;
a first contact coupled to the source region, wherein the first contact comprises a tungsten material above a first barrier layer;
a second contact coupled to the drain region, wherein the second contact comprises a tungsten material above a second barrier layer; and

a second transistor comprising:
a substrate, wherein the substrate comprises silicon fin;
a first dielectric layer on the substrate, wherein the first dielectric layer comprises silicon and oxygen;
a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises hafnium and oxygen;
a pair of gate spacers on the substrate, wherein the gate spacers comprise a dielectric material;
a NMOS metal gate electrode above the second dielectric material and between the pair of gate spacers, wherein the NMOS metal gate electrode comprises:
a barrier layer on the high k dielectric material, wherein the barrier layer comprises titanium and nitrogen;
a tungsten-containing gate fill material on the titanium-containing barrier material;

a source region proximate to one of the pair of gate spacers, and a drain region proximate the other one of the pair of gate spacers, wherein the source region and the drain region comprise an n-type dopant;
a first contact coupled to the source region, wherein the first contact comprises a tungsten material above a first barrier layer; and
a second contact coupled to the drain region, wherein the second contact comprises a tungsten material above a second barrier layer.

10. The device of claim 9 , wherein the assembly comprises a portion of an integrated circuit.

Assignees

• Intel Corp

Inventors

• Pradhan Sameer S
• Bergstrom Daniel B
• Chun Jin-Sung
• Chiu Julia

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L29/4966

  Electricity · mapped topic

• C22C30/00 Primary

  Alloys containing less than 50% by weight of each constituent · CPC title

• H01L29/0653

  Electricity · mapped topic