Magnetic field shielding for packaging build-up architectures
US-9345184-B2 · May 17, 2016 · US
US9580301B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9580301-B2 |
| Application number | US-201314411537-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 29, 2013 |
| Priority date | Jul 6, 2012 |
| Publication date | Feb 28, 2017 |
| Grant date | Feb 28, 2017 |
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Official abstract text for this publication.
A MEMS chip ( 100 ) includes a silicon substrate layer ( 110 ), a first oxidation layer ( 120 ) and a first thin film layer ( 130 ). The silicon substrate layer includes a front surface ( 112 ) for a MEMS process and a rear surface ( 114 ), both the front surface and the rear surface being polished surfaces. The first oxidation layer is mainly made of silicon dioxide and is formed on the rear surface of the silicon substrate layer. The first thin film layer is mainly made of silicon nitride and is formed on the surface of the first oxidation layer. In the above MEMS chip, by sequentially laminating a first oxidation layer and a first thin film layer on the rear surface of a silicon substrate layer, the rear surface is effectively protected to prevent the scratch damage in the course of a MEMS process. A manufacturing method for the MEMS chip is also provided.
Opening claim text (preview).
What is claimed is: 1. A MEMS chip, comprising: a silicon substrate layer comprising a front surface for a MEMS process and a rear surface opposite to the front surface, wherein both the front surface and the rear surface are polished surfaces; a first oxidation layer mainly made of SiO 2 formed on the rear surface of the silicon substrate layer; and a first thin film layer mainly made of silicon nitride formed on a surface of the first oxidation layer; a second oxidation layer formed on the front surface of the silicon substrate layer; a ratio of a thickness of the first oxidation layer to a thickness of the first thin film layer ranges from 3 to 4; wherein the combined stress between the first thin film layer and the first oxidation layer is compensated by the second oxidation layer such that the chip is flat; wherein the first thin film layer and the first oxidation layer are adapted to protect the rear surface of the silicon substrate layer during formation of second oxidation layer and layers applied subsequent to the second oxidation layer. 2. The MEMS chip according to claim 1 , wherein the thickness of the first oxidation layer is 400 nm, the thickness of the first thin film layer is 100 nm, a thickness of the second oxidation layer is 100 nm. 3. The MEMS chip according to claim 1 , further comprising a second thin film layer formed on a surface of the second oxidation layer, wherein the second oxidation layer has the same thickness as that of the first oxidation layer, the second thin film layer has the same thickness as that of the first thin film layer.
Processes for creating layers of materials not provided for in groups B81C1/00357 - B81C1/00373 · CPC title
Depositing a protective layers · CPC title
Protection against environmental influences not provided for in groups B81B7/0012 - B81B7/0025 · CPC title
Protect against mechanical threats, e.g. against shocks, or residues (B81C1/00261 take precedence) · CPC title
by adding further layers of materials having complementary strains, i.e. compressive or tensile strain · CPC title
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