Display device with glass frit sealing portion

US9577215B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9577215-B2
Application numberUS-201414562993-A
CountryUS
Kind codeB2
Filing dateDec 8, 2014
Priority dateJul 9, 2014
Publication dateFeb 21, 2017
Grant dateFeb 21, 2017

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display device includes: a substrate on which a display is formed; an encapsulation portion covering the substrate; and a sealing portion arranged between the substrate and the encapsulation portion and surrounding the display, wherein at least one power wire passes between the substrate and the encapsulation portion, and wherein a metal layer is formed between the sealing portion and the at least one power wire.

First claim

Opening claim text (preview).

What is claimed is: 1. A display device comprising: a substrate; a display disposed on the substrate; an encapsulation portion disposed over the substrate; and a sealing portion comprising a glass frit arranged between the substrate and the encapsulation portion, and surrounding the display, wherein at least one power wire is disposed between the substrate and the encapsulation portion, contacts the sealing portion, and includes a plurality of openings, and wherein an insulating member is disposed in the plurality of openings, and wherein a metal layer is disposed between the sealing portion and the at least one power wire. 2. The display device of claim 1 , wherein the metal layer covers the insulating member. 3. The display device of claim 2 , wherein the metal layer is disposed on a location corresponding to a location where the insulating member is disposed. 4. The display device of claim 1 , wherein the at least one power wire directly contacts at least one portion of the metal layer. 5. The display device of claim 1 , wherein the substrate comprises an active area where the display is disposed, a circuit area extended outside the active area, and a cell seal area extended outside the circuit area, wherein a circuit wire that is electrically connected to the active area is disposed in the circuit area, and wherein the at least one power wire is electrically connected to the circuit wire and receives external power. 6. The display device of claim 5 , wherein the at least one power wire passes a sealing area from the circuit area and is extended to an edge of the substrate. 7. The display device of claim 6 , wherein the at least one power wire is arranged on a different layer from the circuit wire, and wherein at least some portions of the at least one power wire overlap the circuit wire. 8. The display device of claim 1 , wherein the display comprises: at least one thin film transistor (TFT) comprising a semiconductor active layer, at least one gate electrode, at least one source electrode, and at least one drain electrode; and an organic light-emitting display device (OLED) electrically connected to the at least one TFT and comprising a first electrode, an intermediate layer, and a second electrode, and wherein the at least one power wire includes the same material as the at least one source electrode and the at least one drain electrode. 9. The display device of claim 8 , wherein the metal layer includes the same material as the first electrode. 10. The display device of claim 8 , wherein an insulating layer is disposed between the semiconductor active layer, the at least one gate electrode, the at least one source electrode, and the at least one drain electrode in order to insulate the same. 11. The display device of claim 10 , wherein at least one gate wire passes a lower portion of the sealing portion. 12. The display device of claim 11 , wherein the at least one gate wire is arranged on a different layer due to the insulating layer. 13. The display device of claim 1 , wherein the at least one power wire directly contacts at least some portions of the metal layer. 14. The display device of claim 1 , wherein a reinforcement member is further disposed outside the sealing portion. 15. A method of manufacturing a display device, the method comprising: forming a substrate; forming a display on the substrate; covering the substrate with an encapsulation portion; arranging a sealing portion comprising a glass frit between the substrate and the encapsulation portion, and surrounding the display; and forming a plurality of openings in the at least one power wire, and forming an insulating member in the plurality of openings, wherein at least one power wire is disposed between the substrate and the encapsulation portion, and contacts the sealing portion, and wherein a metal layer is disposed between the sealing portion and the at least one power wire. 16. The method of manufacturing of claim 15 , wherein the at least one power wire directly contacts at least some portions of the metal layer. 17. The method of manufacturing of claim 15 further comprising forming a reinforcement member outside the sealing portion, wherein the reinforcement member comprises a sealant. 18. The method of manufacturing of claim 15 , wherein the display comprises: at least one thin film transistor (TFT) comprising a semiconductor active layer, a gate electrode, a source electrode, and a drain electrode; and an organic light-emitting display device (OLED) electrically connected to the at least one TFT and comprising a first electrode, an intermediate layer, and a second electrode, and wherein the at least one power wire includes the same material as the source electrode and the drain electrode. 19. A display device comprising: a substrate; a display disposed on the substrate, wherein the display comprises: at least one thin film transistor (TFT) comprising a semiconductor active layer, at least one gate electrode, at least one source electrode, and at least one drain electrode; and an organic light-emitting display device (OLED) electrically connected to the at least one TFT and comprising a first electrode, an intermediate layer, and a second electrode, and wherein the at least one power wire includes the same material as the at least one source electrode and the at least one drain electrode; an encapsulation portion disposed over the substrate; and a sealing portion comprising a glass frit arranged between the substrate and the encapsulation portion, and surrounding the display, wherein at least one power wire is disposed between the substrate and the encapsulation portion, and contacts the sealing portion, and wherein a metal layer is disposed between the sealing portion and the at least one power wire.

Assignees

Inventors

Classifications

  • Vertical spacers, e.g. arranged between the sealing arrangement and the OLED · CPC title

  • H10K59/131Primary

    Interconnections, e.g. wiring lines or terminals · CPC title

  • Peripheral sealing arrangements, e.g. adhesives, sealants · CPC title

  • Vertical spacers, e.g. arranged between the sealing arrangement and the OLED · CPC title

  • Peripheral sealing arrangements, e.g. adhesives, sealants · CPC title

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Frequently asked questions

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What does patent US9577215B2 cover?
A display device includes: a substrate on which a display is formed; an encapsulation portion covering the substrate; and a sealing portion arranged between the substrate and the encapsulation portion and surrounding the display, wherein at least one power wire passes between the substrate and the encapsulation portion, and wherein a metal layer is formed between the sealing portion and the at …
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10K59/131. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 21 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).