Semiconductor device including landing pad

Patent metadata

Field	Value
Publication number	US-9576902-B2
Application number	US-201615240156-A
Country	US
Kind code	B2
Filing date	Aug 18, 2016
Priority date	Jan 28, 2014
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A semiconductor device includes conductive lines spaced from a substrate, and an insulating spacer structure between the conductive lines and defining a contact hole. The insulating spacer structure is adjacent a side wall of at least one of the conductive lines. The device also includes an insulating pattern on the conductive lines and insulating spacer structure, and another insulating pattern defining a landing pad hole connected to the contact hole. A contact plug is formed in the contact hole and connects to the active area. A landing pad is formed in the landing pad hole and connects to the contact plug. The landing pad vertically overlaps one of the pair of conductive line structures.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate that has an active area;
a pair of conductive line structures on the substrate and including insulating spacer structures respectively formed on side walls thereof;
an insulating pattern on the pair of conductive line structures and each of the insulating spacer structures;
a contact forming conductive layer connected to the active area and between the pair of conductive line structures;
a landing pad forming conductive layer that contacts a top surface of the contact forming conductive layer; and
a landing pad connected to a top surface of the landing pad forming conductive layer and vertically overlapping one conductive line structure of the pair of conductive line structures.

2. The semiconductor device of claim 1 , wherein:
each conductive line structure of the pair of conductive line structures includes an insulating capping line,
a bottom surface of the insulating pattern covers top surfaces of the insulating spacer structure and the insulating capping line in a direction substantially parallel to a plane that extends from a main surface of the substrate.

3. The semiconductor device of claim 1 , wherein a height of a surface of the landing pad forming conductive layer that contacts the landing pad is lower than a height of an uppermost surface of the insulating pattern.

4. The semiconductor device of claim 1 , wherein:
the landing pad forming conductive layer contacts the contact forming conductive layer, and
a size of a width between the landing pad forming conductive layer and the contact forming conductive layer in a direction substantially parallel to a plane that extends from a main surface of the substrate is greater than a size of a width of the contact forming conductive layer between the pair of conductive line structures in the direction substantially parallel to the plane that extends from the main surface of the substrate.

5. The semiconductor device of claim 1 , wherein the contact forming conductive layer includes a same material as a material of the landing pad forming conductive layer.

6. The semiconductor device of claim 1 , further comprising:
a metal silicide film on a bottom surface and a side surface of the landing pad that contact the landing pad forming conductive layer.

7. The semiconductor device of claim 6 , further comprising:
a barrier film on a side wall of the landing pad and a top surface of the metal silicide film.

8. A semiconductor device comprising:
a substrate that has an active area;
a pair of bit line structures on the substrate and including air spacer structures respectively formed on side walls thereof;
an insulating pattern on the pair of bit line structures and each of the air spacer structures;
a contact forming conductive layer connected to the active area and between the pair of bit line structures;
a landing pad forming conductive layer that contacts a top surface of the contact forming conductive layer; and
a landing pad connected to a top surface of the landing pad forming conductive layer and vertically overlapping one bit line structure of the pair of bit line structures.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Je-Min
• Hwang Yoo-Sang

Classifications

• H10W72/90

  Bond pads, in general · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H10B12/482

  Bit lines · CPC title

• H10B12/0335

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title